DDR3 Dynamic ODT on C6657 EVM

Sei Kato

Hi,

I'm looking into the DDR3 initialization process of C6657 EVM.

I found the initialization code example in the GEL file "mcsdk_2_01_02_06/tools/program_evm/gel/evmc6657l.gel", and it enables Dynamic ODT with RZQ/2 (SDCFG.DYN_ODT=0x2) and sets RZQ/2 to DDR_TERM (SDCFG.DDR_TERM=0x2) as follows.

ddr3_setup_auto_lvl_1333()
{
    ....

    /* DDR_SDCFG    = 0x63077AB3; */
    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32;    // last config write DRAM init occurs */
    TEMP = 0;
    TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
    TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
    TEMP |= 0x2 << 24; // DDR_TERM bit field 26:24
    TEMP |= 0x2 << 21; // DYN_ODT bit field 22:21
    TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
    TEMP |= 0x3 << 16; // CWL bit field 17:16
    TEMP |= 0x1 << 14; // NM bit field 15:14
    TEMP |= 0xE << 10; // CL bit field 13:10
    TEMP |= 0x5 << 7; // ROWSIZE bit field 9:7
    TEMP |= 0x3 << 4; // IBANK bit field 6:4
    TEMP |= 0x0 << 3; // EBANK bit field 3:3
    TEMP |= 0x2; // PAGESIZE bit field 2:0
    DDR_SDCFG = TEMP;

    ....
}

With these settings, both Rtt_nom and Rtt_WR of the extended mode registers will be configured to RZQ/2 and then there would no benefit to use Dynamic ODT, isn't it ? Or is there any reason to enable Dynamic ODT with these settings ?

Thanks,
Sei Kato

over 11 years ago

0 Senthilkumar Srinivasan over 11 years ago

TI__Mastermind 43660 points

Hello Sei,

Rtt_Nom takes the DDR3 termination resistor value from SDRAM Config register and Rtt_WR takes the Dynamic ODT value from SDRAM Config Register. To my understanding, DDR3 consider termination resistor value when ODT is disabled and takes Dynamic ODT value when ODT is enabled.

However, i am not very sure why both the register are at same value in the above code. I will check on this and get back to you.

Regards,
Senthil

0 Sei Kato over 11 years ago in reply to Senthilkumar Srinivasan

Prodigy 180 points

Thanks, Senthil

I also noticed that the EVM schematic shows that DDRODT0 pin is connected to two DDR3 chips' ODT pins, and DDRODT1 pin is left open.

But SPRUGV8E Keystone Architecture DDR3 Memory Controller User's Guide recommends to connect DDRODT0 and DDRODT1 to each chip as shown in Figure 3.1. for two 16M x16 x8 banks.

Another question arises; why the EVM does not take the recommended design and is there any relevance to DYN_ODD / DDR_TERM settings above ?

Regards,
Sei Kato

0 Sei Kato over 11 years ago in reply to Sei Kato

Prodigy 180 points

Hi Senthil,

According to the following post, the EVM design seems to be correct on DDRODT0/1 routing since it's using the single rank system.

e2e.ti.com/.../430744

Then Figure 3-1 on SPRUGV8E seems to be wrong, and there's no relevance to DYN_ODT / DDR_TERM settings, I guess.

Thanks,
Sei Kato

0 Tom Johnson 16214 over 11 years ago in reply to Sei Kato

TI__Mastermind 46460 points

Sei,

The document DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B) contains a discussion on recommended impedances in section 4.5. It shows that we recommend DYN_ODT to be disabled. The ODT signal control from the DDR3 controller is sufficient for SDRAM writes.

Please follow the recommendations in the document KeyStone I DDR3 Initialization Application Report (SPRABL2D). It was updated several months back to correct the leveling registers for C665x devices. It also discusses the recommendations for DYN_ODT. Associated with this Application note is the 2 spreadsheets named PHY_CALC and REG_CALC. The latest version of PHY_CALC properly identifies the leveling registers for C665x. The REG_CALC spreadsheet provides assistance with calculating the registers including the SDCFG register including the DYN_ODT setting. The REG_CALC spreadsheet agrees with the Design Requirements in recommending that DYN_ODT be disabled.

The GEL excerpts shown previously in this thread must be from old version of the software. Please make sure that you are using the latest MCSDK release. Additionally, the GEL files are maintained separate from the MCSDK packages and released through EMU packs that can be pulled through CCS.

You can download this update manually. The latest Keystone1 emupack release 1.0.9.1 and is now available at
http://software-dl.ti.com/sdoemb/sdoemb_public_sw/ti_emupack_keystone1/latest/index_FDS.html. you can also get the release from CCS by clicking “Help” -> “Check for Updates” and select keystone 1 emupack package.

The latest version of the C6657 GEL file matches our other documentation and correctly disables DYN_ODT.

Thanks for pointing out that Figure 3-1 in the Keystone Architecture DDR3 Memory Controller User's Guide (SPRUGV8E) is not correct. Figure 3-3 has the same mistake. This is correctly shown in in the Design Guidelines document. It is also defined in the JEDEC spec. ODT0 must be routed to all SDRAMs in the first rank. In dual-rank designs, ODT1 must be routed to all SDRAMS in the second rank. In designs with only one rank, ODT1 will be left unconnected.

Tom

0 Sei Kato over 11 years ago in reply to Tom Johnson 16214

Prodigy 180 points

Hi Tom,

Thank you for the information.

I have downloaded the emupack 1.0.9.1 and got the latest version of the C6657 GEL file.

I confirmed that the DYN_ODT is disabled and RZQ/6 is used for DDR_TERM as recommended in SPRABI1B.
But in the latest version, SDRAM_DRIVE setting has been changed from RZQ/7 (0x1, 34ohms) to RZQ/6 (0x0, 40ohms) though RZQ/7 is recommedned in SPRABI1B. The difference is not significant and both settings would work fine and it's okay for me. But I would like to know if you have some reasons to take RZQ/6 instead of RZQ/7 anyway.

I also noticed that in 4.5.2.1 Data Group Signals for KeyStone II Devices in SPRABI1B, it says that:

It is recommended that the SDRAM be implemented with a 240ohms RZQ resistor and be configured to present an ODT of RZQ/6 for an effective termination of 60ohms.

but RZQ/4 (60ohsms) would be correct as shown in Figure 14.

Anyhow now it's clear to me not to use DYN_ODT, and I can go forward.

Thanks,
Sei Kato

0 Tom Johnson 16214 over 11 years ago in reply to Sei Kato

TI__Mastermind 46460 points

Sei,

You are correct. The GEL does program it to 0x0 which equates to an SDRAM_DRIVE strength of RZQ/6 or 40 ohms. The SPRABL2D and SPRABI2B documents, which are more general for all KeyStone I devices, recommend RZQ/7 or 34 ohms. Both values will work in the supported topologies. In general C665x devices have smaller topologies since they only support a 32-bit DDR3 interface whereas C667x devices have much larger topologies often having 64 bits of data plus ECC. The higher drive strength (lower impedance) is better matched to larger topologies having longer traces and more crosstalk.

You are correct that there is an error in 4.5.2.1 Data Group Signals of SPRABI2B. The sentence should read: "It is recommended that the SDRAM be implemented with a 240 ohm RZQ resistor and be configured to present an ODT of RZQ/4 for an effective termination of 60 ohms."

Tom

0 Gk 110 over 9 years ago in reply to Tom Johnson 16214

Expert 2440 points

Hi Tom-san

I found this thread.

You already confirmed mistake Figure3-1(and Figure3-3) 2 years ago.

However it doesn't correct yet.
Our customers also referenced the user's guide(SPRUGV8E) and made a mistake in connection.

Could you please correct Figure3 in the SPRUGV8E in the near future.

Best regards,

Gk110

Processors

Processors forum

DDR3 Dynamic ODT on C6657 EVM