Hello everyone,
I am working on DM37xEVM and want to establish a PCM communication interface between TPS65950 and DM3730. I have some questions to ask.
I have configured codec for PCM Tx and Rx. I am writing raw data (a sine wave) to DXR of McBSP3. I have selected path 1 but do not hear anything on headphones neither notice a wave on oscilloscope. I have attached my codec initialization. My McBSP3 initialization is as follows:
/* Enable McBSP3 functional clock. */
temp32 = MEM_READ32(0x48005000);
MEM_WRITE32(0x48005000, temp32|2);
/* Enable McBSP3 interface clock. */
temp32 = MEM_READ32(0x48005010);
MEM_WRITE32(0x48005010, temp32|2);
/* Place McBSP in reset state. */
MEM_WRITE32(0x49024014, 0x00);
MEM_WRITE32(0x49024010, 0x00);
/* Required configuration. */
MEM_WRITE32(0x49024048, 0x000); //PCR
MEM_WRITE32(0x49024024, 0x40); //XCR1
MEM_WRITE32(0x49024020, 0x0040); //XCR2
MEM_WRITE32(0x490240AC, 1<<11); //XCCR
MEM_WRITE32(0x4902401C, 0x40); //RCR1
MEM_WRITE32(0x49024018, 0x8040); //RCR2
/* Threshold control register. */
MEM_WRITE32(0x49024090, 0x400);
/* Take it out of reset. */
MEM_WRITE32(0x49024014, 0x01);
MEM_WRITE32(0x49024010, 0x01);
I want to take input from MIC. In my initialization, I enable AUXL and AUXR inputs of MIC. When I read the DRR, I see data like:
0
18
0
3e
ffde
0
0
4e
fffa
0
4c
2a
10
0
ffe2
38
0
0
26
ffe8
0
ffca
0
fff0
24
c
0
0
20
24
0
28
0
10
0
ffdc
0
e
20
0
18
0
fffc
2e
0
10
0
2
1e
0
8
0
0
c
28
0
0
38
ffe0
0
40
0
ff
1. I want to ask if there is some special configuration required for PCM operation which I am missing?
2. I am reading data from DRR and writing it to DXR until there is space in transmit fifo. Is it a correct way of hearing what I speak?
3. In I2S, we write raw data to DXR and audio gets played in headphones. Is this same true for PCM as well or it is required to format data before writing to DXR?
Kindly help me as I am not able to get PCM working.
Thanks,
Muhammad Umair Khan
/* Function prototypes */
UINT8 twl4030_read(UINT8 addr, UINT8 reg);
VOID twl4030_write(UINT8 addr, UINT8 reg, UINT8 value, UINT8 mask);
/* Codec initialization routine. */
void Codec_Init()
{
/* Ensure Codec is powered down */
if (twl4030_read (twl4030, CODEC_MODE) & CODECPDZ)
{
twl4030_write (twl4030, HS_POPN_SET, 0, RAMP_EN);
twl4030_write (twl4030, HS_GAIN_SET, 0, 0xF);
twl4030_write (twl4030, HS_POPN_SET, 0, VMID_EN);
twl4030_write (twl4030, CODEC_MODE, 0, CODECPDZ);
}
/* Set FS rate */
twl4030_write (twl4030, CODEC_MODE, 0x0, OPT_MODE); /* Mode 0 */
twl4030_write (twl4030, CODEC_MODE, 0x0, SEL_16K); /* Voice mode: 8Khz */
twl4030_write (twl4030, CODEC_MODE, APLL_RATE_48000, APLL_RATE_MASK);
/* Enable RX left/right, TX left/right, Enable Voice RX left, Voice TX left */
twl4030_write (twl4030, OPTION, (ARXR2_EN | ARXL2_EN | ATXR1_EN | ATXL1_EN | ARXL1_VRX_EN | ATXL2_VTXL_EN), 0xFF);
/* Route to RXL1 and RXR1 PGA */
twl4030_write (twl4030, RX_PATH_SEL, RXL1_SEL_SDRL2_RXL1PGA | RXR1_SEL_SDRR2_RXR1PGA, RX_SEL_MSK);
/* Config input Clock Frequency */
twl4030_write (twl4030, APLL_CTL, APLL_INFREQ_26, APLL_INFREQ_MASK);
twl4030_write (twl4030, APLL_CTL, APLL_EN, APLL_EN);
twl4030_write (twl4030, BOOST_CTL, BOOST_CTL_EFFECT_1, BOOST_CTL_EFFECT_1 | BOOST_CTL_EFFECT_0);
/* Enable Audio DACs */
twl4030_write (twl4030, AVDAC_CTL, ADACL1_EN | ADACR1_EN | VDAC_EN, ADACL1_EN | ADACR1_EN | VDAC_EN);
/* Config Analog RXL1 PGA control */
twl4030_write (twl4030, ARXL1_APGA_CTL, ARXL1_DA_EN | ARXL1_PDZ | ARXL1_GAIN_SET_0DB,
ARXL1_DA_EN | ARXL1_PDZ | ARXL1_GAIN_SET_MASK);
/* Config Analog RXR1 PGA control */
twl4030_write (twl4030, ARXR1_APGA_CTL, ARXR1_DA_EN | ARXR1_PDZ | ARXR1_GAIN_SET_0DB, ARXR1_DA_EN | ARXR1_PDZ | ARXR1_GAIN_SET_MASK);
/* Enable softvol sweep time of 1024 * 0.8/FS */
twl4030_write (twl4030, SOFTVOL_CTL, 0, SOFTVOL_SET_MASK);
twl4030_write (twl4030, SOFTVOL_CTL, SOFTVOL_EN, SOFTVOL_EN);
/* Slave mode, 16-bit words, */
twl4030_write (twl4030, AUDIO_IF, AIF_SLAVE_EN | CLK256FS_EN, AIF_SLAVE_EN | CLK256FS_EN | DATA_WIDTH_MASK | AIF_FORMAT_MASK);
twl4030_write (twl4030, AUDIO_IF, AIF_EN, AIF_EN);
/* VOICE CONFIG FOR BT */
twl4030_write (twl4030, VOICE_IF, 0x69, 0xFF);
/* Enabel Headset Audio L/R1 */
twl4030_write (twl4030, HS_SEL, HSOL_AL1_EN | HSOR_AR1_EN, HSOL_MSK);
/* Set the Digital PGA HeadSet volume to 0db */
twl4030_write (twl4030, ARXL1PGA, 0x3f, 0xff);
twl4030_write (twl4030, ARXR1PGA, 0x3f, 0xff);
/* Set Voice gain to 0db */
twl4030_write (twl4030, VRXPGA, 0x25, 0xFF);
twl4030_write (twl4030, HS_GAIN_SET, HS_GAIN_SETL_0DB | HS_GAIN_SETR_0DB, 0xF);
/* Enable Pop reduction on analog gain changes (delay until zero cross) */
twl4030_write (twl4030, MISC_SET_1, SMOOTH_ANAVOL_EN, SMOOTH_ANAVOL_EN);
/* Select Analog inputs */
twl4030_write (twl4030, ADCMICSEL, 0, 0);
/* Enable Aux inputs left/right */
twl4030_write (twl4030, ANAMICL, AUXL_EN | MICAMPL_EN, AUXL_EN | MICAMPL_EN | OFFSET_CNCL_SEL_0 | OFFSET_CNCL_SEL_1);
twl4030_write (twl4030, ANAMICR, AUXR_EN | MICAMPR_EN, AUXR_EN | MICAMPR_EN);
/* Enable Audio ADC */
twl4030_write (twl4030, AVADC_CTL, ADCL_EN | ADCR_EN, ADCL_EN | ADCR_EN);
/* Set the initial AuxIn Volume */
twl4030_write (twl4030, ATXL1PGA, 0x09, 0x1f);
twl4030_write (twl4030, ATXR1PGA, 0x09, 0x1f);
/* Enable ADCs */
twl4030_write (twl4030, AVADC_CTL, ADCL_EN | ADCR_EN, 0xFF);
/* Mute Digital Loopback */
twl4030_write (twl4030, ATX2ARXPGA, 0x0, 0x3f);
/* As per Codec doc's toggle the Power to apply reg setting */
twl4030_write (twl4030, CODEC_MODE, 0, CODECPDZ); /* Power down Codec */
twl4030_write (twl4030, CODEC_MODE, CODECPDZ, CODECPDZ); /* Power Up Codec */
/* To prevent clipping of the negative portion of the audio output */
twl4030_write (twl4030, HS_POPN_SET, VMID_EN | (1 << 2), VMID_EN | RAMP_DELAY_MASK);
twl4030_write (twl4030, HS_POPN_SET, RAMP_EN, RAMP_EN);
}
