DM814x McASP loopback test

Muhammad Tariq

Other Parts Discussed in Thread: TMS320C6727, CCSTUDIO

hello everyone,

I am trying to modify a test code of Mcasp Loopback TMS320c6727 for Mcasp of DM814x nd for that i have done some alterations in the header files ,command files but i am getting some errors,which i am not able to rectify.kindly help in this regards.i am also attaching my c files nd header files.the errrors i am getting are :

undefined first referenced

symbol in file

--------- ----------------

_McASP0 ./main.obj

_McASP1 ./main.obj

_McASP2 ./main.obj

error #10234-D: unresolved symbols remain

error #10010: errors encountered during linking; "D710 McASP.out" not built

/*
 * main.c
 */
#include  "DM814x.h"
#include "McASP_definitions.h"
#include "McASP_functions.c"
#include "stdio.h"
#include "string.h"

char result[256]={"0"};

void clearResult()
{
	int i=0;
	for(i=0; i<255; i++)
		result[i]=' ';
}

void formatResult(int error)
{
	clearResult();
	if(error==1)
		strcpy(result, "McASP Loopback passed");
	else strcpy(result, "McASP Loopback failed");
}

void finalStep(void)
{
	while(1);
}

int main(void) {
	initMcASP_I2S_Loopback(0); // Loopback on McASP0
	// initMcASP_I2S(0); // I2S on Ser0
	int status=0;
	int i=0;
	for(i=0; i<256; i++)
	{
		status=checkLoop(0x01234567, 0x89ABCDEF); // reading loopback data; returns 0 if pass, 1 if fail
		//ckeckI2S(0x01234567, 0x89ABCDEF);  / left and right data
		if(status==2)
			i=256;
	}
	if(status==0)
		status=1;
	formatResult(status);
	finalStep();
	return 0;
}




extern far int McASP0[0xFFF];
extern far int McASP1[0xFFF];
extern far int McASP2[0xFFF];


//L3 Mem Map//
//size of  MCASP0,1,2 data peripheral registers 4MB//
#define MCASP0_BASE_ADDRESS        0x46000000
#define MCASP0_END_ADDRESS         0x463FFFFF

#define MCASP1_BASE_ADDRESS        0x46400000
#define MCASP_END_ADDRESS          0x467FFFFF

#define MCASP2_BASE_ADDRESS        0x46800000
#define MCASP2_END_ADDRESS         0x46BFFFFF

//size of McASP3,4,5 data peripheral registers 4KB
//L4 Mem map
#define MCASP3_Cortex_A8_BASE_ADDRESS             0x4A1A5000
#define MCASP3_Cortex_A8_END_ADDRESS              0x4A1A5FFF

#define MCASP4_Cortex_A8_BASE_ADDRESS             0x4A1AB000
#define MCASP4_Cortex_A8_END_ADDRESS              0x4A1ABFFF

#define MCASP5_Cortex_A8_BASE_ADDRESS             0x4A1B1000
#define MCASP5_Cortex_A8_END_ADDRESS              0x4A1B1FFF


#define BUFFER_CFGRD_WFIFOCTL        0x48039000
#define BUFFER_CFGRD_WFIFOSTS        0x48039004
#define BUFFER_CFGRD_RFIFOCTL        0x48039008
#define BUFFER_CFGRD_RFIFOSTS        0x4803900C

#define PID	    (0x00/4)
#define PWRDEMU 	(0x04/4)
#define REV         (0x00/4)
#define PFUNC		(0x10/4)
#define PDIR		(0x14/4)
#define PDOUT		(0x18/4)
#define PDIN		(0x1C/4)
#define PDSET		(0x1C/4)
#define PDCLR		(0x20/4)

#define GBLCTL 		(0x44/4)
#define AMUTE		(0x48/4)
#define DLBCTL		(0x4C/4)
#define DITCTL		(0x50/4)

#define RGBCTL		(0x60/4)
#define RMASK		(0x64/4)
#define RFMT		(0x68/4)
#define AFSRCTL		(0x6C/4)
#define ACLKRCTL	(0x70/4)
#define AHCLKRCTL	(0x74/4)
#define RTDM		(0x78/4)
#define RINTCTL		(0x7C/4)
#define RSTAT		(0x80/4)
#define RSLOT		(0x84/4)
#define RCLKCHK		(0x88/4)
#define REVTCTL		(0x8C/4)

#define XGBLCTL		(0xA0/4)
#define XMASK		(0xA4/4)
#define XFMT		(0xA8/4)
#define AFSXCTL		(0xAC/4)
#define ACLKXCTL	(0xB0/4)
#define AHCLKXCTL	(0xB4/4)
#define XTDM		(0xB8/4)
#define XINTCTL		(0xBC/4)
#define XSTAT		(0xC0/4)
#define XSLOT		(0xC4/4)
#define XCLKCHK		(0xC8/4)
#define XEVTCTL		(0xCC/4)

#define DITCSRA0 	(0x100/4)
#define DITCSRA1 	(0x104/4)
#define DITCSRA2 	(0x108/4)
#define DITCSRA3 	(0x10C/4)
#define DITCSRA4 	(0x110/4)
#define DITCSRA5 	(0x114/4)
#define DITCSRB0 	(0x118/4)
#define DITCSRB1 	(0x11C/4)
#define DITCSRB2 	(0x120/4)
#define DITCSRB3 	(0x124/4)
#define DITCSRB4 	(0x128/4)
#define DITCSRB5 	(0x12C/4)
#define DITUDRA0	(0x130/4)
#define DITUDRA1	(0x134/4)
#define DITUDRA2	(0x138/4)
#define DITUDRA3	(0x13C/4)
#define DITUDRA4	(0x140/4)
#define DITUDRA5	(0x144/4)
#define DITUDRB0	(0x148/4)
#define DITUDRB1	(0x14C/4)
#define DITUDRB2	(0x150/4)
#define DITUDRB3	(0x154/4)
#define DITUDRB4	(0x158/4)
#define DITUDRB5	(0x15C/4)

#define SRCTL0		(0x180/4)
#define SRCTL1		(0x184/4)
#define SRCTL2		(0x188/4)
#define SRCTL3		(0x18C/4)
#define SRCTL4		(0x190/4)
#define SRCTL5		(0x194/4)
#define SRCTL6		(0x198/4)
#define SRCTL7		(0x19C/4)
#define SRCTL8		(0x1A0/4)
#define SRCTL9		(0x1A4/4)
#define SRCTL10		(0x1A8/4)
#define SRCTL11		(0x1AC/4)
#define SRCTL12		(0x1B0/4)
#define SRCTL13		(0x1B4/4)
#define SRCTL14		(0x1B8/4)
#define SRCTL15		(0x1BC/4)

#define XBUF0 		(0x200/4)
#define XBUF1 		(0x204/4)
#define XBUF2 		(0x208/4)
#define XBUF3 		(0x20C/4)
#define XBUF4 		(0x210/4)
#define XBUF5 		(0x214/4)
#define XBUF6 		(0x218/4)
#define XBUF7 		(0x21C/4)
#define XBUF8 		(0x220/4)
#define XBUF9 		(0x224/4)
#define XBUF10 		(0x228/4)
#define XBUF11		(0x22C/4)
#define XBUF12		(0x230/4)
#define XBUF13		(0x234/4)
#define XBUF14		(0x238/4)
#define XBUF15		(0x23C/4)

#define RBUF0 		(0x280/4)
#define RBUF1 		(0x284/4)
#define RBUF2 		(0x288/4)
#define RBUF3 		(0x28C/4)
#define RBUF4 		(0x290/4)
#define RBUF5 		(0x294/4)
#define RBUF6 		(0x298/4)
#define RBUF7 		(0x29C/4)
#define RBUF8 		(0x2A0/4)
#define RBUF9 		(0x2A4/4)
#define RBUF10 		(0x2A8/4)
#define RBUF11		(0x2AC/4)
#define RBUF12		(0x2B0/4)
#define RBUF13		(0x2B4/4)
#define RBUF14		(0x2B8/4)
#define RBUF15		(0x2BC/4)






#include "McASP_definitions.h"

static void delayCycles(int i)
{
	for(;i>0; i--);
}

static void initMcASP_beginn(int McASP)
{
	if(McASP==0)
	{
		McASP0[GBLCTL]=0x0;
		McASP0[PWRDEMU]=0x1;
	}
	if(McASP==1)
		{
			McASP1[GBLCTL]=0x0;
			McASP1[PWRDEMU]=0x1;
		}
	if(McASP==1)
		{
			McASP1[GBLCTL]=0x0;
			McASP1[PWRDEMU]=0x1;
		}
}

static void initMcASP_RX(int McASP, int RnX, int MASK, int FMT, int AFSCTL, int ACLKCTL, int AHCLKCTL, int TDM, int INTCTL, int CLKCHK) // RnX=0 Transmit, 1 Receive
{
	if(McASP==0)
	{
		if(RnX==0)
		{
			McASP0[XMASK]=MASK;
			McASP0[XFMT]= FMT;
			McASP0[AFSXCTL]= AFSCTL;
			McASP0[ACLKXCTL]= ACLKCTL;
			McASP0[AHCLKXCTL]= AHCLKCTL;
			McASP0[XTDM]= TDM;
			McASP0[XINTCTL]= INTCTL;
			McASP0[XCLKCHK]= CLKCHK;
		}
		else
		{
			McASP0[RMASK]=MASK;
			McASP0[RFMT]= FMT;
			McASP0[AFSRCTL]= AFSCTL;
			McASP0[ACLKRCTL]= ACLKCTL;
			McASP0[AHCLKRCTL]= AHCLKCTL;
			McASP0[RTDM]= TDM;
			McASP0[RINTCTL]= INTCTL;
			McASP0[RCLKCHK]= CLKCHK;
		}
	}
	else if(McASP==1)
	{
		if(RnX==0)
		{
			McASP1[XMASK]=MASK;
			McASP1[XFMT]= FMT;
			McASP1[AFSXCTL]= AFSCTL;
			McASP1[ACLKXCTL]= ACLKCTL;
			McASP1[AHCLKXCTL]= AHCLKCTL;
			McASP1[XTDM]= TDM;
			McASP1[XINTCTL]= INTCTL;
			McASP1[XCLKCHK]= CLKCHK;
		}
		else
		{
			McASP1[RMASK]=MASK;
			McASP1[RFMT]= FMT;
			McASP1[AFSRCTL]= AFSCTL;
			McASP1[ACLKRCTL]= ACLKCTL;
			McASP1[AHCLKRCTL]= AHCLKCTL;
			McASP1[RTDM]= TDM;
			McASP1[RINTCTL]= INTCTL;
			McASP1[RCLKCHK]= CLKCHK;
		}
	}
	else if(McASP==2)
	{
		if(RnX==0)
		{
			McASP2[XMASK]=MASK;
			McASP2[XFMT]= FMT;
			McASP2[AFSXCTL]= AFSCTL;
			McASP2[ACLKXCTL]= ACLKCTL;
			McASP2[AHCLKXCTL]= AHCLKCTL;
			McASP2[XTDM]= TDM;
			McASP2[XINTCTL]= INTCTL;
			McASP2[XCLKCHK]= CLKCHK;
		}
		else
		{
			McASP2[RMASK]=MASK;
			McASP2[RFMT]= FMT;
			McASP2[AFSRCTL]= AFSCTL;
			McASP2[ACLKRCTL]= ACLKCTL;
			McASP2[AHCLKRCTL]= AHCLKCTL;
			McASP2[RTDM]= TDM;
			McASP2[RINTCTL]= INTCTL;
			McASP2[RCLKCHK]= CLKCHK;
		}
	}
}

static void initMcASP_Ser(int McASP, int MODEh, int MODEl, int DRIVEh, int DRIVEl) // rebundle from settings in each int to settings for each serializer. LSB of int always stands for serializer 0, only lower 16 Bit used
{
	int buf=0;
	int count=0;
	for(count=0; count<15; count++)
	{
		buf=0;
		if(((DRIVEh >> count) & 1) == 1)
		buf++;
		buf = buf << 1;
		if(((DRIVEl >> count) & 1) == 1)
		buf++;
		buf = buf << 1;
		if(((MODEh >> count) & 1) == 1)
		buf++;
		buf = buf << 1;
		if(((MODEl >> count) & 1) == 1)
		buf++;
		if(McASP==0)
		McASP0[SRCTL0+count]=buf;
		if(McASP==1)
		McASP1[SRCTL0+count]=buf;
		if(McASP==2)
		McASP2[SRCTL0+count]=buf;
	}
}

static void initMcASP_Pins(int func, int dir)
{
	McASP0[PFUNC]= McASP0[PFUNC] | func;
	McASP0[PDIR]= McASP0[PDIR] | dir;
}

static void initMcASP_stuff(int McASP, int DIT, int LOOP, int MUTE)
{
	if(McASP==0)
	{
		McASP0[DITCTL]= DIT; 		// DIT mode
		McASP0[DLBCTL]= LOOP; 		// Loopback
		McASP0[AMUTE]= MUTE; 		// AMUTE
	}
	if(McASP==1)
		{
			McASP1[DITCTL]= DIT; 		// DIT mode
			McASP1[DLBCTL]= LOOP; 		// Loopback
			McASP1[AMUTE]= MUTE; 		// AMUTE
		}
	if(McASP==2)
		{
			McASP2[DITCTL]= DIT; 		// DIT mode
			McASP2[DLBCTL]= LOOP; 		// Loopback
			McASP2[AMUTE]= MUTE; 		// AMUTE
		}
}

static void initMcASP_buffer(int ASP, int val)
{
	int j=0;
	for(j=0; j<15; j++)
	{
		if(ASP==0)
			McASP0[XBUF0 +j]= val;		// Sending val in the first transmission
		if(ASP==1)
			McASP1[XBUF0 +j]= val;
		if(ASP==2)
			McASP2[XBUF0 +j]= val;
	}
}

static void initMcASP_launch(int McASP)
{
	if(McASP==0)
	{
		McASP0[GBLCTL]= McASP0[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
		while(!(McASP0[GBLCTL] & 0x202));
		delayCycles(1000);
		McASP0[GBLCTL]= McASP0[GBLCTL] | 0x101; // Enable RCLK and XCLK
		while(!(McASP0[GBLCTL] & 0x101));
		delayCycles(1000);
		McASP0[XSTAT]= 0xFFFF;		// Clear all status registers
		McASP0[RSTAT]= 0xFFFF;
		McASP0[GBLCTL]= McASP0[GBLCTL] | 0x404; // Enable Serializers
		while(!(McASP0[GBLCTL] & 0x404));
		delayCycles(1000);
		initMcASP_buffer(McASP, 0x5F0AF50A);
		McASP0[GBLCTL]= McASP0[GBLCTL] | 0x808; // Enable State Machines
		while(!(McASP0[GBLCTL] & 0x808));
		delayCycles(1000);
		McASP0[GBLCTL]= McASP0[GBLCTL] | 0x1010; // Enable Frame Syncs
		while(!(McASP0[GBLCTL] & 0x1010));
	}
	if(McASP==1)
	{
		McASP1[GBLCTL]= McASP1[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
		while(!(McASP1[GBLCTL] & 0x202));
		delayCycles(1000);
		McASP1[GBLCTL]= McASP1[GBLCTL] | 0x101; // Enable RCLK and XCLK
		while(!(McASP1[GBLCTL] & 0x101));
		delayCycles(1000);
		McASP1[XSTAT]= 0xFFFF;		// Clear all status registers
		McASP1[RSTAT]= 0xFFFF;
		McASP1[GBLCTL]= McASP1[GBLCTL] | 0x404; // Enable Serializers
		while(!(McASP1[GBLCTL] & 0x404));
		delayCycles(1000);
		initMcASP_buffer(McASP, 0x5F0AF50A);
		McASP1[GBLCTL]= McASP1[GBLCTL] | 0x808; // Enable State Machines
		while(!(McASP1[GBLCTL] & 0x808));
		delayCycles(1000);
		McASP1[GBLCTL]= McASP1[GBLCTL] | 0x1010; // Enable Frame Syncs
		while(!(McASP1[GBLCTL] & 0x1010));
	}
	if(McASP==2)
	{
		McASP2[GBLCTL]= McASP2[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
		while(!(McASP2[GBLCTL] & 0x202));
		delayCycles(1000);
		McASP2[GBLCTL]= McASP2[GBLCTL] | 0x101; // Enable RCLK and XCLK
		while(!(McASP2[GBLCTL] & 0x101));
		delayCycles(1000);
		McASP2[XSTAT]= 0xFFFF;		// Clear all status registers
		McASP2[RSTAT]= 0xFFFF;
		McASP2[GBLCTL]= McASP2[GBLCTL] | 0x404; // Enable Serializers
		while(!(McASP2[GBLCTL] & 0x404));
		delayCycles(1000);
		initMcASP_buffer(McASP, 0x5F0AF50A);
		McASP2[GBLCTL]= McASP2[GBLCTL] | 0x808; // Enable State Machines
		while(!(McASP2[GBLCTL] & 0x808));
		delayCycles(1000);
		McASP2[GBLCTL]= McASP2[GBLCTL] | 0x1010; // Enable Frame Syncs
		while(!(McASP2[GBLCTL] & 0x1010));
	}
}

static void initMcASP_I2S(int ASP) // transmitt I2S on Ser0
{
	initMcASP_beginn(ASP);
	initMcASP_RX(ASP, 0, 0xFFFFFFFF, 0x180F8, 0x112, 0x3F, 0x8000, 0x03, 0x0, 0xFF0005);
	initMcASP_Ser(ASP, 0, 1, 0, 0); //Ser0 is Transmitter, TRI-State
	initMcASP_Pins(0, 0x1E00000F);
	initMcASP_stuff(ASP, 0, 0, 0);
	initMcASP_launch(ASP);
}

static void initMcASP_I2S_Loopback(int ASP) // transmitt I2S on even Serializers, receive on odd
{
	initMcASP_beginn(ASP);
	initMcASP_RX(ASP, 0, 0xFFFFFFFF, 0x180F8, 0x112, 0x3F, 0x8000, 0x03, 0x0, 0xFF0005);
	initMcASP_RX(ASP, 1, 0xFFFFFFFF, 0x180F8, 0x112, 0x3F, 0x8000, 0x03, 0x0, 0xFF0005);
	initMcASP_Ser(ASP, 0xAAAA, 0x5555, 0, 0); //Even Ser Transmitter, odd receive, TRI-State
	initMcASP_Pins(0, 0xFF00FFFF);
	initMcASP_stuff(ASP, 0, 0x7, 0);
	initMcASP_launch(ASP);
}

static int checkLoop(int left, int right) // only for McASP0!
{
	int i=0;
	int error=0;
	while((McASP0[SRCTL0] & 0x00000010) != 0x00000010); // ready to transmit new data?
	if(McASP0[XSTAT] & 0x8) // even channel number? (left or right for I²S)
	{
		for(i=0; i<15; i++)
		{
			McASP0[XBUF0 +i]=left;
			i++;
		}
	}
	else
	{
		for(i=0; i<15; i++)
		{
			McASP0[XBUF0+i]=right;
			i++;
		}
	}
	int read=0;
	while((McASP0[SRCTL1] & 0x00000020) != 0x00000020); // new data available?
	for(i=1; i<15; i++)
	{
		read = McASP0[XBUF0 +i];
		if((read != left) && (read != right) && (read != 0x5F0AF50A))
			error=2; // set breakpoint here for error detection! ******************************************************************
		i++;
	}
	return error;
}

static void checkI2S(int left, int right)
{
		while((McASP0[SRCTL0] & 0x00000010) != 0x00000010); // ready to transmit new data?
		if(McASP0[XSTAT] & 0x8) // even channel number? (left or right for I²S)
			McASP0[XBUF0]=left;
		else
			McASP0[XBUF0]=right;
}
/*
static void initMcASP0(void) // example initialization with fixed values for I2S, not using the variable initialization methods
{
	McASP0[GBLCTL]=0x0;
	McASP0[PWRDEMU]=0x1;
	McASP0[XMASK]=0xFFFFFFFF; 	// No replacing of Bits
	McASP0[XFMT]= 0x180F8; 		// 01 delay, 1 MSB First, 0 Pad, 0 value, 0xF SlotSize 32, 1 Peripheral Bus, 000 no rotation
	McASP0[AFSXCTL]= 0x112; 	// 0x2 Slots, 00 reserved, 1 Word, 00 reserved, 1 internal, 0 rising edge
	McASP0[ACLKXCTL]= 0x3F;		// 0 rising edge, 0 Sync, 1 internal, 0x1F Divide by 32
	McASP0[AHCLKXCTL]= 0x8000;	// 1 internal, 0 rising edge, 00 reserved, 0 divide AUXCLK by 1
	McASP0[XTDM]= 0x3; 			// slots 0 and 1 active
	McASP0[XINTCTL]= 0x0; 		// no interrupts
	McASP0[XCLKCHK]= 0xFF0005; 	// 0xFF maximum, 0x00 minimum, 0 autoswitch disabled, 000 reserved, 0x5 prescaler 32
	McASP0[SRCTL0]= 0x1;		// 0 RRDY, 0 XRDY, 0 3-State, 01 Transmitter
	McASP0[PFUNC]= 0x0; 		// McASP occupies all Pins
	McASP0[PDIR]= McASP0[PDIR] | 0x1E00000F; 	// 1E00000F Frame Sync, HCLK, CLK, AMUTE AXR0-7 as Outputs for McASP0
	McASP0[DITCTL]= 0x0; 		// DIT mode disabled
	McASP0[DLBCTL]= 0x0; 		// Loopback disabled
	McASP0[AMUTE]= 0x0; 		// AMUTE disabled
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x202; // Enable RHCLK and XHCLK
	while(!(McASP0[GBLCTL] & 0x202));
	delayCycles(1000);
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x101; // Enable RCLK and XCLK
	while(!(McASP0[GBLCTL] & 0x101));
	delayCycles(1000);
	McASP0[XSTAT]= 0xFFFF;		// Clear all status registers
	McASP0[RSTAT]= 0xFFFF;
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x404; // Enable Serializers
	while(!(McASP0[GBLCTL] & 0x404));
	delayCycles(1000);
	McASP0[XBUF0]= 0x5F0AF50A;		// Sending AAAA in the first comand
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x808; // Enable State Machines
	while(!(McASP0[GBLCTL] & 0x808));
	delayCycles(1000);
	McASP0[GBLCTL]= McASP0[GBLCTL] | 0x1010; // Enable Frame Syncs
	while(!(McASP0[GBLCTL] & 0x1010));
}
*/

over 9 years ago

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Hi Tariq,

Are you trying to create .out file in CCStudio project, where you have GEL file + c/h files?

Or are you trying to create linux user space application that will run on top of linux kernel?

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

yes i am trying to create an .out file in CCS studio project

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

Tariq,

In lines 5 and 209 you include the same h file McASP_definitions.h, can you remove this file include operation in line 209.

Also in line 6 you include c file (McASP_functions.c) instead of h file. Can you try to replace the c file with its h file?

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

actually i think you didnt get it.....these are different files like main.c,McASP_definitions.h,and McASP_definitions.c......nd i have pasted all three files here in one comment

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

D710 McASP.zip

please fine the attached project folder

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

Tariq,

In main.c file from your project folder, in line 6 I still see you include C file instead of H file. Can you fix that? What is the result then?

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

i have removed c file but still its not working besides sorry i didnt understand what header file do you want me to replace with .c file ?these are the errors coming after removing the .c file from the main

Description Resource Path Location Type
#10010 errors encountered during linking; "D710 McASP.out" not built D710 McASP C/C++ Problem

Description Resource Path Location Type
unresolved symbols remain D710 McASP C/C++ Problem

Description Resource Path Location Type
unresolved symbol _checkLoop, first referenced in ./main.obj D710 McASP C/C++ Problem

Description Resource Path Location Type
unresolved symbol _initMcASP_I2S_Loopback, first referenced in ./main.obj D710 McASP C/C++ Problem

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

Tariq,

Do you need this code to compile and run on the DM814x Cortex-A8 ARM or C674x DSP?

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

on dm814x cotex arm a8

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

The project you have attached invokes C67xx compiler, not A8 ARM compiler.

I would recommend you to start from the DM814x McASP CCS test as a base and modify it according to your use case.

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

yes i mentioned in the start ,this test code was for TSM320c6727 nd i altered it for dm814x but i have also tried to run it over dsp core of c672x ,still it doesnt work.....
besides can you provide me any pointer from where i should start for arm cortex a8 or is there any way to change the above for a8 as

0 Pavel Botev over 9 years ago in reply to Muhammad Tariq

TI__Guru**** 170625 points

I would recommend you to start with McASP code from Mistral:

www.mistralsolutions.com/.../tmdxevm8148.html

Software -> Diagnostic software -> Base Bord -> Rev D -> CCS_Test_code -> aic3106

Software -> Diagnostic software -> Expansion I/O Board -> Rev D -> CCS_Test_Code -> IOExpansion_Application -> spdif

BR
Pavel

0 Muhammad Tariq over 9 years ago in reply to Pavel Botev

Intellectual 320 points

sure thanx

Processors

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DM814x McASP loopback test