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DDR3 placement for Keystone II (66AK2E02)

suhas dk
Prodigy 110 points

Hi All,

Can the DDR3 devices for the Keystone II processor (66AK2E02)  be placed opposite sides of PCB (top-bottom).

I have used 4 DDR3 Devices as a single rank design & placed 2 devices on TOP and another 2 devices in bottom. Somebody please confirm whether this is  acceptable for proper functionality.

Regards,

Suhas D K.

  • 0
    TI__Mastermind 43660 points
    Hello Suhas,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    As long as the DDR3 Design Guidelines are adhered to, yes they can be placed on opposite sides of the PCB. There will be routing constraints that will need to be adhered to that are specified in the DDR3 Design Guidelines.

    www.ti.com/.../sprabi1b.pdf

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 110 points

    Thank you  Mr.Senthil,

    We have placed the devices in top and bottom due to place constraint. But In the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B) it is mentioned that "It is strongly recommended that all SDRAMs are mounted on the top side of the PCB alongside the SoC for single rank designs." can you please let me know is there any specific reason for this.

     

    Regards,

    Suhas D K.

  • 0 in reply to suhas dk
    TI__Mastermind 43660 points
    Hello Suhas,

    I believe routing the DDR3 memory devices on both top and bottom is an acceptable implementation. There are multiple designs in production that have this layout. This can best be accomplished by using buried or blind via stack-ups including those with micro-vias. The fly-by routing topology must still be met. All fly-by nets must follow the same basic route and connect to the SDRAMs in the same order and with similar stub lengths.

    Actually in Rev A of the DDR3 Design Requirements document, it was stated like DDR3 devices can be placed in both top and bottom. But in Rev B document, the statement is revised like you mentioned above. I am not sure about the reason behind this. I will try to get more insight on this and update you. Thanks for your patience until then.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 110 points

    Dear Mr. senthil,

    Thanks for the reply,

    As you mentioned "There are multiple designs in production that have this layout" Can u please point  us to any of those designs which is in production, having this kind of (Top & Bottom)implementation, which will help us in further understanding & implementation.Since K2E EVM is having DDR3 SODIMM module. we didn't get clear idea about the DDR3 Fly-by topology implementation in Keystone II based design.

    Regards,

    Suhas  DK.

  • 0 in reply to suhas dk
    TI__Mastermind 43660 points
    Hello Suhas,

    The multiple designs that i mentioned are customer designs. We do not have those designs to share with you. The K2H EVM board has on board DDR3 chips in addition to the DIMM. You could consider this design for your reference.

    Regards,
    Senthil
  • 0 in reply to suhas dk
    TI__Mastermind 43660 points
    Hello Suhas,

    The statement in the document, Placing all of the SDRAMs for a single rank on one side of the board is only a recommendation and not requirement. It is possible to implement a top and bottom placement for a single rank but it is very difficult to do so and to meet the routing requirements. The board must have many layers to support the required track routing for top and bottom SDRAM placement.

    Regards,
    Senthil