SDRAM trouble

Hi,
What is your emulator ?
Able to connect successfully even for one time ?

Able to run simple hello world program on SDRAM ?

Hello Titus,

1) Emulator SAU510-USB IsoPlus v2
2) Emulator Connect successfully.
3) Simple hello world program doesn't work on SDRAM. Without SDRAM all programs works successfully.

Try to enable "Adaptive Clocking" in target configuration.

I am enable "Adaptive Clocking" but the error remained the same.

C674X_0: File Loader: Verification failed: Values at address 0x00000000C0006920 do not match Please verify target memory and memory map.

C674X_0: GEL: File: C:\ti\Workspace\McASP_EDMA\Debug\McASP_EDMA.out: a data verification error occurred, file load failed.

I am added  the  some information:

I am configured a cmd  file for writing to SHDSPL2RAM. Then I am  tried to write in SDRAM  at address 0xC000 0000 -> it's work successfully.

But  addresses only available 0xC000 0000 -> 0xC0FFFFFC (16MBit).

My SDRAM chip - 64Mb / 4M x 16 bit.

I am hope for your help.

Thanks.

Hi,

c6747 DSP Startup Sequence

C674X_0: GEL Output: Setup PINMUX Registers...C674X_0: GEL Output: [Done]

C674X_0: GEL Output: PLL Setup Complete

C674X_0: GEL Output: Setup Power Modules (All on)...C674X_0: GEL Output: [Done]

C674X_0: GEL Output: SDRAM Complete

C674X_0: GEL Output:

Startup Complete.

After connecting the target, able to access the SDRAM memory (C0000000) through CCS memory browser ?

I have attached the test.out, please try it and let me know the result.

Test_C6745.zip

Hello Titus S,

Great Thanks for your help.

I am run the attached test.out and have the following result:

I tried to write into a cell 0xC0000000  - it's work successfully, but  only available range of addresses: 0xC0000000  -> 0xC7FFFFFF.

Thanks.

Hi,
Your problem got resolved ?

but only available range of addresses: 0xC0000000 -> 0xC7FFFFFF.

For C6747, you can interface 256MiB SDRAM address and for C6745, only 128MiB SDRAM can access as per the C6745 memory map from data sheet.

I'm sorry, I was wrong:

Available range of addresses: 0xC0000000 -> 0xC0FFFFFC (16MBit) - only 1 bank.
I checked my circuit and pcb - it's OK.
My problem doesn't resolved.

Hi,

I tried to write into a cell 0xC0000000 - it's work successfully, but only available range of addresses: 0xC0000000 -> 0xC7FFFFFF.

How did you execute this code for writing on SDRAM address ?
Internal RAM used ?

What are all the things you modified in gel file ?
Have you modified the correct SDRAM parameters as per your SDRAM data sheet ?

Hi,

I am using Internal RAM.
I am modified gel file (Pinmux, Pll, PSC).
I am modified the correct SDRAM parameters per my SDRAM data sheet.


Setup_EMIFB()
{
// AS4C4M16S-7TCN SDRAM, 1M x 16 (16-bit data path), 133MHz
EMIFB_SDCFG = 0 // SDRAM Bank Config Register
|( 1 << 15) // Unlock timing registers
|( 1 << 14) // Narrow Mode (16bits wide)
|( 2 << 9 ) // CAS latency is 2
|( 2 << 4 ) // 4 bank SDRAM devices
|( 2 << 0 ); // 1024-word pages requiring 10 column address bits

EMIFB_SDREF = 0 // SDRAM Refresh Control Register
|( 0 << 31) // Low power mode disabled
|( 0 << 30) // MCLK stoping disabled
|( 0 << 23) // Selects self refresh instead of power down
|( 1040 <<0); // Refresh rate = 7812.5ns / 7.5ns

EMIFB_SDTIM1 = 0 // SDRAM Timing Register 1
|( 8 << 25) // (67.5ns / 7.55ns) - 1 = TRFC @ 133MHz
|( 2 << 22 ) // (20ns / 7.5ns) - 1 =TRP
|( 2 << 19 ) // (20ns / 7.5ns) - 1 = TRCD
|( 1 << 16 ) // (14ns / 7.5ns) - 1 = TWR
|( 5 << 11 ) // (45ns / 7.5ns) - 1 = TRAS
|( 8 << 6 ) // (67.5ns / 7.5ns) - 1 = TRC
|( 2 << 3 ); // *(((4 * 14ns) + (2 * 7.5ns)) / (4 * 7.5ns)) -1. = TRRD
// but it says to use this formula if 8 banks but only 4 are used here.
// and SDCFG1 register only suports upto 4 banks.

EMIFB_SDTIM2 = 0 // SDRAM Timing Register 2
|( 14<< 27) // not sure how they got this number. the datasheet says value should be
// "Maximum number of refresh_rate intervals from Activate to Precharge command"
// but has no equation. TRASMAX is 120k.
|( 9 << 16) // ( 70 / 7.5) - 1
|( 5 << 0 ); // ( 45 / 7.5 ) - 1

EMIFB_SDCFG = 0 // SDRAM Bank Config Register
|( 1 << 16)
|( 1 << 14) // Narrow Mode (16bits wide)
|( 0 << 15) // Unlock timing registers
|( 2 << 9 ) // CAS latency is 2
|( 2 << 4 ) // 4 bank SDRAM devices
|( 2 << 0 ); // 1024-word pages requiring 10 column address bits

GEL_TextOut( "SDRAM Setup Complete\n" );




I noticed a strange behavior on pins: BA0, BA1 (Bank Activate).
When I read the memory in memory browser from 0xC0000000 to 0xC0FFFFFC - I see multiple signal change on the above pins.

When I read the memory in memory browser from 0xC0FFFFFC to 0xC7FF FFFF - signal doesn't change on the above pins.

I am find the mistake in gel file:

GEL_MapAddStr( 0xC0000000, 0, 0x01000000, "R|W|AS4", 0 ); it was

GEL_MapAddStr( 0xC0000000, 0, 0x10000000, "R|W|AS4", 0 ); now

Now i can write and read in any cell from 0xC0000000 to 0xC3FFFFFF -> 64MBit (cmd file configured to work with SHDSPL2RAM).

But when I configured cmd file to work with EMIFBSDRAM I get an error:
C674X_0: File Loader: Verification failed: Values at address 0x00000000C0006920 do not match Please verify target memory and memory map.
C674X_0: GEL: File: C:\ti\Workspace\McASP_EDMA\Debug\McASP_EDMA.out: a data verification error occurred, file load failed.


I don't understand where taken this [0x00000000C0006920] address ?
I'm at an impasse.


I am hope for your help.
Thanks.

Hi,
Try to access (read & write) this SDRAM address "0xC0006920", check the memory map of that project (*.map).
1) Can you tried default gel file ?
2) Just change the SDRAM timing parameters in gel file and try.

Hi,

1) Yes, but I have the same error.

2) I change the SDRAM timing parameters, but this does not solve the problem.

       EMIFB_SDTIM1 = 0        // SDRAM Timing Register 1

       |( 7 << 25)         // (63ns / 7.55ns) - 1 = TRFC  @ 133MHz

       |( 2 << 22 )        // (21ns / 7.5ns) - 1 =TRP

       |( 2 << 19 )        // (21ns / 7.5ns) - 1 = TRCD

       |( 1 << 16 )        // (14ns / 7.5ns) - 1 = TWR

       |( 5 << 11 )        // (49ns / 7.5ns) - 1 = TRAS

       |( 7 <<  6 )        // (63ns / 7.5ns) - 1 = TRC

       |( 1 <<  3 );       // (14ns/7.5ns) -1 = TRRD

Hi Alex,
Sounds good.
Thanks for your update.