CCS V6 SEARCH OPTION IN WHOLE PROJECT

Hi Naveen,

 AISgen tool acts as an interface between CCS studio V6 and external SPI Flash.!!!

Step 1 : Build the DSP code by using main.c , device.c and device.h!!
Step 2: After building compiler will give me file_name.out!!
Step 3: Load this file_name.out into the AISgen tool in the appication column by selecting the file path.
Step 4: In the files option select configure for EVM and then the AISgen tool genrates .bin file.
Step 5: Load this .bin file to UartHost tool which will generate image file.
step 6: Load this image file to SDRAM using the emulator.

Upto step4, its fine.
Then you have to flash this *.bin to flash (NAND or NOR or SPI) as per your settings used in AISgen tool.
After that set correspond boot mode to  boot your application.

 1. How do i do EMIFB initilization through gel file?? Please let me know the steps..!! what exactly do you mean by gel file??
  I hope my questions are clear to you. Can i manually configure and initialize EMIFB settings?? Also, how do i make use of this gel file.

If you are using EVM board then you no need to worry about anything, by defaut EMIFB initialization had been done in gel file.
Please refer to the gel file "Setup_EMIFB();"
If you want to boot from SDRAM (EMIFB) just configure the linker command file (*.cmd) of that DSP project.

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Hi Naveen,

I want to flash the image file in my SPI flash memory. SPI flash memory is my external device.

How do you want to boot ?

I want to boot it from my SDRAM which is also a external device.

You want to boot from SPI and should run on SDRAM right ?

If you want to boot from SDRAM (EMIFB) just configure the linker command file (*.cmd) of that DSP project!!

how do i configure the linker command file(*.cmd)??? Where it will be available.

You have linker command file in your project which has .cmd extension, it will declare the code where to  execute whether its from SDRAM or internal RAM (L2RAM, shared RAM etc.,)

Ex:

The following linker command file (*.cmd) tells to compiler that the code going to run on internal L2 RAM.

-lrts64plus.lib

-stack          0x00001000 /* Stack Size */  

MEMORY
{
	L2RAM		org=0x80010000 len=0x00010000 /* L2 RAM/Cache */
}

SECTIONS
{
	.text       > L2RAM
	.const      > L2RAM
	.bss        > L2RAM
	.far		> L2RAM
	.switch		> L2RAM
	.stack      > L2RAM
	.data       > L2RAM
	.cinit		> L2RAM
	.sysmem		> L2RAM
	.cio		> L2RAM
}

Ex:

The following linker command file (*.cmd) tells to compiler that the code going to run on external RAM (SDRAM).

-lrts64plus.lib

-stack          0x00001000 /* Stack Size */  

MEMORY
{
	L2RAM		org=0x80010000 len=0x00010000 /* L2 RAM/Cache */
    EMIFBSDRAM   org = 0xC0000000  len = 0x10000000     /* 256MB SDRAM Data */                   

}

SECTIONS
{
	.text       > EMIFBSDRAM
	.const      > EMIFBSDRAM
	.bss        > EMIFBSDRAM
	.far		> EMIFBSDRAM
	.switch		> EMIFBSDRAM
	.stack      > EMIFBSDRAM
	.data       > EMIFBSDRAM
	.cinit		> EMIFBSDRAM
	.sysmem		> EMIFBSDRAM
	.cio		> EMIFBSDRAM
}

Please refer to the gel file "Setup_EMIFB();"
where do i find this function call in my project?? Where do i find this content??

You don't find it in your project, it will be available in gel file which you are using before loading the program through emulator.

C:\ti\ccsv5\ccs_base\emulation\boards\evmomapl137\gel\evmomapl137_dsp.gel

I hope this helps.

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Hi Naveen,

Naveen said:

Am waiting for your inputs for my above queries. Also, i wanted to know whether we can port SYS/BIOS for DSP core of OMAPL137 and linux os for ARM9 core?? As i was going through the datasheet it says DSP/BIOS will support for OMAPL137 and SYS/BIOS is the new version of DSP/BIOS.

Yes, your understanding is right here.Yes, you can run SYS/BIOS on DSP core and Linux on ARM core.

I have a feeling that you are repeatedly asking multiple questions on a same thread, which will get defocus on your orignial question.

For OMAPL137, there is a QuickStartOMAPL1x rCSL package. There is a detailed TI WIKI for it: , Please go through it completely.

Open up a new query as appending questions on the same thread will get least priority compared to new threads.

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