AM3352 SD_SYSCONFIG

shankar sm

Other Parts Discussed in Thread: SYSCONFIG

Hi,

We are using BBB(am335x) based custom board with a Marvell's Wifi chip. We are using linux-3.12.10 kernel.

I was referring the AM335x TRM section 18.4.1.1 SD_SYSCONFIG under Multimedia Card Registers. I see from the register settings that bits 31 - 10 are reserved and have a default value of 0h. However when I read the register I see that the value is 0x2015

1. Why is Bit 13 set?

2. I have a wifi chip connected to MMC-SDIO and I am trying to get the MMC-SDIO clk to be free running. I tried changing the values of this register using devmem2 app and read back as set which is 0x230C (AUTO_IDLE - off, SIDDLE_MODE=1h, CLOCKACTIVITY=3h). But there was no effect on the clock. What am I missing?

Thanks

Shankar

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

shankar sm said:
1. Why is Bit 13 set?

Bits marked as "reserved" in the register documentation have no end-user functionality and should not be changed.

shankar sm said:
2. I have a wifi chip connected to MMC-SDIO and I am trying to get the MMC-SDIO clk to be free running. I tried changing the values of this register using devmem2 app and read back as set which is 0x230C (AUTO_IDLE - off, SIDDLE_MODE=1h, CLOCKACTIVITY=3h). But there was no effect on the clock. What am I missing?

I will ask the MMC experts if this is possible and how to do it.

0 shankar sm over 10 years ago in reply to Biser Gatchev-XID

Prodigy 210 points

Hi Biser,
Thanks for the reply. Did you get a chance to check with the MMC experts on point 2?
Your help is much appreciated.

Thanks
Shankar

0 Biser Gatchev-XID over 10 years ago in reply to shankar sm

TI__Guru**** 393215 points

I have asked. Feedback will be posted directly here when available.

0 Brad Griffis over 10 years ago in reply to Biser Gatchev-XID

TI__Guru*** 125430 points

Nearly all peripherals in the device have a SYSCONFIG register, and this register's purpose is to control auto-gating of clocks *internal* to the device. Forcing a clock to stay on internal to the device will not directly equate to forcing the pin to stay on at the bus level. It looks to me like the other pertinent bits are SD_CON[CLKEXTFREE] and SD_SYSCTL[CEN].

0 shankar sm over 10 years ago in reply to Brad Griffis

Prodigy 210 points

Thanks Brad. That solved my issue :)

Processors

Processors forum

AM3352 SD_SYSCONFIG