I am currently running the DM368 PLL2 with a ratio of 18 (M=9, N=0) with a 24 Mhz crystal to get a clock of 432 MHz. However, I need to have the Voice Codec run at 16 KHz. According to the example in Table 3-6 of the TMS320DM368 (SPRS668C), the PLL2 configuration needs to change to a ratio of 448/25 (M=224, N=24) to get a clock of 430.08 for the 16 KHz clock. I changed the setting of the PLL2 in the device.c file of the UBL to match. With the change, the UBL would no longer successfully load UBoot. I changed the PLL2 setting back to a the original ratio of 18 and booted successfully. I then used different values of M and N while maintaining the ratio of 18. I found that the UBL would work with M=27 and N=2. However, when I change to M=36 and N=3 (ratio still 18), the UBL would no longer load and transfer to Uboot. It appears as if the UBL read of the header from Nand Flash for uboot is corrupted.
Are there additional settings necessary to change the clock to 430.08Mhz? What is the sensitivity to changing M and N while maintaining the same ratio? Any help would be appreciated.
Thanks
