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What is the reason of EDMA performance on DDR A and DDR B different on EVM K2H?

Peter010
Genius 4165 points
Other Parts Discussed in Thread: 66AK2H12

Hello everyone

We have one EVMK2H12. Our project is communication time constraint. So, the performance of EDMA is crucial to our application. As we have EVMK2H12, so we plan to use ARM cores to handle the data communication. On the ARM core of EVMK2H12, we use register level configuration to perform EDMA0 from MSMC to DDR without using Linux kernal. The EDMA transmission is manually triggered, and the consumption time is calculated between ESR bit is set and IPR bit is noticed.

The figure showing below are test results. From it, we can see that EDMA has better performance if the data is sending to DDR B. So what is the reason of EDMA has better performance if data is on DDR B?

Thank you

Xining

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    Yes, you are right. DDR3B has better EDMA throughput than DDR3A since DDR3B operates at higher clock @800 MHz than DDR3A operating at 666 MHz. This could be one key reason and also row switch overhead could be the other reason as well.

    In general, the performance of multiple EDMA TCs access different rows on same DDR bank would be much worser than the performance of multiple EDMA TCs access different rows on different DDR banks, the reason could be the DDR row switch overhead. The result would become still worse when DDR load becomes heavy. The worst case is multiple EDMA TCs write to different rows on same DDR bank, which would be almost dominated by the row switch overhead because every write burst result in row switch. Kindly refer Table 13 for the performance of multiple EDMA sharing DDR from the attached memory performance doc. See also. Table 10 for the performance of multiple EDMA sharing MSMC RAM from the attached. As well, see Table 8 for the throughput comparison between TCs on 1.2GHz Keystone II from the same doc.

    /cfs-file/__key/communityserver-discussions-components-files/791/3223.8371.K2-SOC-Memory-Performance.doc

    Usually, the probability of row switch, i.e. multiple master accesses same DDR bank depends on the master number and DDR bank number. So the DDR controller on KeyStone 2 is optimized to get rid of row switch overhead.

    Unlike MSMCRAM having very high bandwidth, the DDR bandwidth (1600 x 8 = 12800MB/s) is not enough for all masters/EDMA TC's access simultaneously, the priority of different masters affects the bandwidth allocation between these masters.

    Thanks & regards,

    Sivaraj K

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    Please click the Verify Answer button on this post if it answers your question.

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  • 0 in reply to Sivaraj Kuppuraj
    Genius 4165 points
    Hi Sivaraj
    Thanks for your replying.

    In the post, you can see that the speed of each DDR is 1333MTS. That means I let DDR3B work at 666MHz, not 800MHz. So, in theory, EDMA should have same performance on DDR3B and DDR3A.

    Regards
    Xining
  • 0 in reply to Peter010
    TI__Mastermind 35645 points
    Hi,

    Yes, you are right.

    DDR3B has slightly better EDMA throughput than DDR3A but theoretically, it would be same.

    Thanks & regards,
    Sivaraj K
  • 0 in reply to Sivaraj Kuppuraj
    Genius 4165 points
    Hi Sivaraj K

    The reason of less performance of using DDR3A is the problem of physical layout of EVM66AK2H12, or the limitation of the chip--66AK2H12.

    Thanks
    Xining
  • 0 in reply to Peter010
    TI__Mastermind 18136 points

    Hi,

    I hope the following comparison DDR3A vs DDR3B helps:

    both support memory widths up to 64 bits.
    both are interconnected with a 256-bit data interface.
    both support memory clock frequencies up to the same rate.

    DDR3A is provided with an internal clock that is cpu/2. MPAX available.
    DDR3B is provided with an internal clock that is cpu/3. No MPAX.

    Externally the theoretical throughput limit is 1600*64=102.4Gbsp.

    Internally the throughput limit of DDR3A for a 1GHz device is 1000/2*256=128Gbps.
    Internally the throughput limit of DDR3B for a 1GHz device is 1000/3*256=85.3Gbps.

    There are performance differences (latency) related to the location since DDR3A is connected to MSMC and
    DDR3B is connected directly to the TeraNet.:
    DDR3A is closer to the cores in that respect.
    DDR3B is closer to the other SoC masters (e.g. EDMA).


    Kind regards,

    one and zero

  • 0 in reply to one and zero
    Genius 4165 points
    Thanks for replying, one and zero.

    From your clarification, it seems that DDR3A should outperform DDR3B. But from my result and the attachment uploaded by Sivaraj K(in the first response), why the performance of DDR3A by using EDMA is less than DDR3B?

    Thanks
    Xining
  • 0 in reply to Peter010
    TI__Mastermind 18136 points

    No. the last paragraph explains why the DDR3B is better for EDMA accesses.

    The reason is that the 2 DDR3 interaces are hooked to differently to the internals of the SoC.

    The DDR3B is connected to the TeraNet which is the interconnect. This suits better when using non core bus masters like the EDMA ...

    The DDR3A is hooked to the MSMC which offers better access to DSP and ARM cores.

    You can also see this in the datasheet.

    Kind regards,

    one and zero.

  • 0 in reply to one and zero
    Genius 4165 points
    Thanks for your clarification.

    On 6678, DDR3 is connected with MSMC same as DDR3A on 66AK2H. From my above chart, the performance of EDMA of accessing DDR3 on 6678 is better than DDR3A on 66AK2H12. So can you explain the reason of this?

    Thanks.
    Xining
  • 0 in reply to Peter010
    TI__Mastermind 18136 points

    Hi Xining,

    the DDR3A performance on C6678 and K2H should be in the same ballpark. However the interconnect architecture is different and will have some impact.

    I don't know how you measured the cycles but one think you need to consider when comparing your numbers. It seems you ran the K2H at 1.2GHz while the C6678 ran at 1GHz. That means that even if the transfer takes that same amount of time on the K2H you'll see more cycles consumed since the core runs faster ...

    Kind regards,

    one and zero