• State Resolved
  • Locked Locked
  • Replies 12 replies
  • Subscribers 101 subscribers
  • Views 1111 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5K2E04 won't go into boundary scan mode

David McIntyre
Prodigy 90 points
Other Parts Discussed in Thread: AM5K2E04

Using Keystone II AM5K2E04 device. Both POR and RESETFULL are pulled low and connected to an FPGA. The FPGA has been programmed to perform the power sequencing and reset to the AM5K2E04 so it drives both low and eventually releases them high. Per the bsdl model the only requirement for boundary scan is that POR be toggled low to high and that both POR and RESETFULL are high. Both EMU0 and EMU1 are floating as are all other EMU pins and there is no warnings that EMU0 and EMU1 be in a defined state for boundary scan, although other TI processors typically have a defined state for EMU0 and EMU1 usually opposite of what is required for emulation mode? The bsdl file did mention a warning about TMS being low before TRST goes high, but a previous TI response said this was in error and would be removed from the bsdl file. What is the correct formula for getting the AM5K2E04 part into boundary scan mode so that we can include it in the boundary scan testing??

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • 0
    TI__Mastermind 42545 points

    Hi David,
    Clock is also required. Are you toggling the clock?
    Regards,
    Bill

  • 0 in reply to Bill Taboada
    Prodigy 90 points
    Which clock is needed, the bsdl design warning section claims clock is not needed
    attribute DESIGN_WARNING of AM5K2E0X : entity is
    " According to simulation, BSD JTAG TAP may not work correctly unless "&
    " device has completed RESET sequence first. "&
    " Forcing POR low then release (no clock pulses required) would meet "&
    " the requirement.
  • 0 in reply to David McIntyre
    TI__Mastermind 42545 points

    Hi David,

    Internally, the device uses the CORECLKP/N to complete the reset sequence. This is shown in Figure 11-1 in the data manual. The CORECLKP/N must be toggling before PORz and RESETFULLz are released as part of the reset sequencing.

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Prodigy 90 points

    We have already verified that we are providing a 100 MHz CORECLKP/N to the device. Also, we have captured the RESETSTAT signal transitioning high following a reset sequence indicating that the device has left the reset state.

  • 0 in reply to David McIntyre
    Prodigy 90 points
    Are there any requirements for EMU00 and EMU01, they are currently no connects ???
  • 0 in reply to David McIntyre
    TI__Mastermind 42545 points
    Earlier C6000 processors required that the EMU0 and EMU1 be low for boundary scan to be active. My understanding was that this requirement was not included for the K2E but I've asked the design team to verify. Have you sampled the TDO to see if there is any activity on the JTAG chain while you are operating boundary scan?
  • 0 in reply to Bill Taboada
    TI__Mastermind 46460 points

    David,

    KeyStone devices have a single, master JTAG TAP for all modes of operation.  Older C6000 devices had multiple JTAG taps that were selected based on the EMU pin configuration.  EMU pin settings have no affect on the JTAG TAP operation.

    What do you mean when you state that it will not go into boundary scan mode?  Does the K2E device JTAG operate correctly with an emulation pod and CCS attached?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 90 points

    Board did not have room for emulator connector so we cannot hook up an emulator. When we run a JTAG capture test where we should get the default

    capture value (000001) out of the instruction register (attribute INSTRUCTION_CAPTURE of AM5K2E0X : entity is "000001"; from bsdl file), instead we

    capture 111111 .

  • 0 in reply to David McIntyre
    TI__Mastermind 46460 points

    David,

    Your observation indicates the JTAG port is non-functional.

    Every boards needs a JTAG test port, even if it is on a reduced footprint connector or simply a DNI header on production boards.  Debug visibility is severely limited without it.  Is the board functional at all or are you trying to validate assembly with boundary scan?

    CCS and emulation can operate over the 5 required signals for JTAG and boundary scan.  You should wire up an adapter to test with an emulation pod.  There are simple JTAG port integrity tests that you need to pass before having any confidence in the boundary scan result.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    David,

    Please see links by opening e2e in your browser.  I did not receive the links in my email copy.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 90 points
    Tried second test adapter and second tactical board and with configured FPGA providing POR reset and then driving POR and RESETFULL high the JTAG capture best now passes. Problem appears to be related to bad TA and/or bad tactical board, another variable is the config clock rate was changed from one TA to another. At any rate, we now know we can get part to respond in JTAG mode. Thanks for all the help and suggestions, especially for confirming that EMU0 and EMU1 are not required for JTAG.