C6678 with 5Gbps PCIe using 100MHz reference clock

Hi,

I want to use C6678 with 5Gbps PCIe using 100MHz PCIECLK. Could I realize this use case?

Yes.

I see the following document. Does this description mean that 2.5GHz PLL output frequency can realize 5Gbps?

Keystone PCIe UG (SPRUGS6D): 2.3.3 Reference Clock Multiplication
"The targeted PLL output frequency (line rate) is 2.5 GHz in both PCIe Gen1 and Gen2 modes."

The targeted PLL output frequency (line rate) is 2.5 GHz in both PCIe Gen1 and Gen2 modes. The PCIe PHY performs data bus width conversion
from 8-bit to 16-bit when the module switches from Gen1 speed to Gen2 speed. The output frequency of the PLL stays constant irrespective of whether it is operating in Gen1 or Gen2 mode. Set the DIR_SPD bit to 1 in the PL_GEN2 register during the initialization can switch the PCIe link speed mode from Gen1 (2.5Gbps) to Gen2 (5.0Gbps).

Refer section 3.9.13 Gen2 Register (PL_GEN2) on PCIe user guide. Based on DIR_SPD bit field LTSSM to initiate a speed change to Gen2 after the link is initialized at Gen1 speed.

Thanks,

Hello Ganapathi,

Thank you for your quick reply.

Can the desired speed for 5Gbps realize as below? LINERATE = 100M * 25 / 1 = 2500Mbps < 5Gbps

- Reference Clock MHz: 100
- PLL Multiplier: 25x (64h)
- PLL Output (MHz): 2500
- Rate Scale: 1
- Line Rate (Mbps): 2500
- DIR_SPD bit in the PL_GEN2 register: 1

How can I change RATESCALE? Is it fixed-value by device? There are some descriptions about rate scale except 1.0. But I can't find configuration register about it.

Regards,
Kazu