We use am3359 EVM board.
We had to modify the PIN configured to use an FPGA, it plans to use to expand the GPMC.
The modified information is as follows.
1. Pin Customized
| Type | Mode | Pin No. | GPIO No. | Pin Name | Signal Name | Mode |
| GPMC | FUNC | A15 | GPIO0_19 | XDMA_EVENT_INTR0 | XDMA_EVENT_INTR0 | 0 |
| GPMC | FUNC | V2 | GPIO0_08 | LCD_DATA12 | GPMC_A16 | 1 |
| GPMC | FUNC | V3 | GPIO0_09 | LCD_DATA13 | GPMC_A17 | 1 |
| GPMC | FUNC | V4 | GPIO0_10 | LCD_DATA14 | GPMC_A18 | 1 |
| GPMC | FUNC | T5 | GPIO0_11 | LCD_DATA15 | GPMC_A19 | 1 |
| GPMC | FUNC | F17 | GPIO2_26 | MMC0_DAT3 | GPMC_A20 | 1 |
| GPMC | FUNC | F18 | GPIO2_27 | MMC0_DAT2 | GPMC_A21 | 1 |
| GPMC | FUNC | G15 | GPIO2_28 | MMC0_DAT1 | GPMC_A22 | 1 |
| GPMC | FUNC | G16 | GPIO2_29 | MMC0_DAT0 | GPMC_A23 | 1 |
| GPMC | FUNC | G17 | GPIO2_30 | MMC0_CLK | GPMC_A24 | 1 |
| GPMC | FUNC | G18 | GPIO2_31 | MMC0_CMD | GPMC_A25 | 1 |
| GPMC | FUNC | U7 | GPIO1_00 | GPMC_AD0 | GPMC_AD0 | 0 |
| GPMC | FUNC | V7 | GPIO1_01 | GPMC_AD1 | GPMC_AD1 | 0 |
| GPMC | FUNC | R8 | GPIO1_02 | GPMC_AD2 | GPMC_AD2 | 0 |
| GPMC | FUNC | T8 | GPIO1_03 | GPMC_AD3 | GPMC_AD3 | 0 |
| GPMC | FUNC | U8 | GPIO1_04 | GPMC_AD4 | GPMC_AD4 | 0 |
| GPMC | FUNC | V8 | GPIO1_05 | GPMC_AD5 | GPMC_AD5 | 0 |
| GPMC | FUNC | R9 | GPIO1_06 | GPMC_AD6 | GPMC_AD6 | 0 |
| GPMC | FUNC | T9 | GPIO1_07 | GPMC_AD7 | GPMC_AD7 | 0 |
| GPMC | FUNC | U10 | GPIO0_22 | GPMC_AD8 | GPMC_AD8 | 0 |
| GPMC | FUNC | T10 | GPIO0_23 | GPMC_AD9 | GPMC_AD9 | 0 |
| GPMC | FUNC | T11 | GPIO0_26 | GPMC_AD10 | GPMC_AD10 | 0 |
| GPMC | FUNC | U12 | GPIO0_27 | GPMC_AD11 | GPMC_AD11 | 0 |
| GPMC | FUNC | T12 | GPIO1_12 | GPMC_AD12 | GPMC_AD12 | 0 |
| GPMC | FUNC | R12 | GPIO1_13 | GPMC_AD13 | GPMC_AD13 | 0 |
| GPMC | FUNC | V13 | GPIO1_14 | GPMC_AD14 | GPMC_AD14 | 0 |
| GPMC | FUNC | U13 | GPIO1_15 | GPMC_AD15 | GPMC_AD15 | 0 |
| GPMC | FUNC | R7 | GPIO2_02 | GPMC_ADVn_ALE | GPMC_ADVN_ALE | 0 |
| GPMC | FUNC | T6 | GPIO2_05 | GPMC_BEn0_CLE | GPMC_BE0N_CLE | 0 |
| GPMC | FUNC | U18 | GPIO1_28 | GPMC_BEn1 | GPMC_BE1N_CLE | 0 |
| GPMC | FUNC | V12 | GPIO2_01 | GPMC_CLK | GPMC_WAIT1 | 2 |
| GPMC | FUNC | V6 | GPIO1_29 | GPMC_CSn0 | GPMC_CS0N | 0 |
| GPMC | FUNC | U9 | GPIO1_30 | GPMC_CSn1 | GPMC_CLK | 1 |
| GPMC | FUNC | V9 | GPIO1_31 | GPMC_CSn2 | GPMC_CS2N | 0 |
| GPMC | FUNC | T13 | GPIO2_00 | GPMC_CSn3 | GPMC_CS3N | 0 |
| GPMC | FUNC | T7 | GPIO2_03 | GPMC_OEn_REn | GPMC_OEN_REN | 0 |
| GPMC | FUNC | T17 | GPIO0_30 | GPMC_WAIT0 | GPMC_WAIT | 0 |
| GPMC | FUNC | U6 | GPIO2_04 | GPMC_WEn | GPMC_WEN | 0 |
| GPMC | FUNC | U17 | GPIO0_31 | GPMC_WPn | GPMC_WPN | 0(7) |
2. Current progress
board-am335xevm.c and mux33xx.c was adapted to the PIN modification.
3. our question
Currently CS 0 is using a NAND partition.
We try to approach the GPMC (FPGA) using the CS 2,3 and wait 1.
Should we be any modifications to the source-code connected to enable GPMC(FPGA) to work?
It is guess to be related to gpmc-nand.c and gpmc.c.
Please guide that if we modify any parts.
