Hi all,
I am working on a project using a TI C6727B running an real-time interrupt-driven task and a lower priority background process (main()). The task runs within the ISR of the NMI, which is triggered by sending a periodic 10 KHz tick to the EM_WAIT input.
Before the background task accesses a critical section, the wait rise interrupt is disabled by writing a 1 to the WRMCLR bit of the EIMCR register. When coming out of the critical sections the interrupt is re-enabled by writing a 1 to the WRMSET bit of the EIMSR register.
My question is: What happens when the wait rise interrupt is disabled and a rising edge is detected on the EM_WAIT input? For what I read, this condition is latched in the EIRR register but, is the NMI triggered when the interrupts are re-enabled or is it lost?
Many thanks,
Raul Murillo
