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PCIe link training failed with PHY loopback

WilliamV
Prodigy 100 points

Hello,

I am developing bare metal application on ARM with a K2L evaluation board. Currently, I am trying to make a PCIe driver to communicate with only one end point (it will be a FPGA), the Keystone is the root complex.

My end point is not available at the moment, so I want to test my driver in loopback mode (PHY) with no hardware connected. I encounter a problem with the link training, the LTSSM state stay in DETECT_QUIET (0x00).

My driver initialises the PCIe 0 lane with the following steps:

  1. Configuration in root complex (DEVCFG)
  2. Disable link training (CMD_STATUS)
  3. Set lane number to x1 (PL_LINK_CTRL)
  4. Set generation 2 for 5 Gb/s (PL_GEN2)
  5. Unlock writing to BAR mask (CMD_STATUS)
  6. Set BAR mask 0 and 1 (respectively 0x0007FFF and 0x0FFFFFFF)
  7. Lock writing to BAR mask (CMD_STATUS)
  8. Enable memory access, mastership bus, poisoned TLP, error message (STATUS_COMMAND)
  9. Enable unsupported request, fatal, non-fatal, correctable errors (DEV_STAT_CTRL)
  10. Enable ECRC (PCIE_ACCR)
  11. Set outbound region size to 8 MB (OB_SIZE)
  12. Clear the outbound region registers (OB_OFFSET_LO/OB_OFFSET_HI)
  13. Set inbound region (IB_BAR/IB_START/IB_OFFSET)
  14. Enable inbound/outbound translation (CMD_STATUS)
  15. Set BAR 0 and 1 (respectively 0x21800000 and 0x80000000)
  16. Enable PHY loopback (SERDES_CFG0 = 0x0010C000)
    1. Enable Rx/Tx loopback
    2. Disable Loss of signal
  17. Enable link training (CMD_STATUS)
  18. For link state for PHY loopback (PL_FORCE_LINK)
    1. Set link state to POLL_ACTIVE
    2. Set FORCE_LINK
  19. Wait for LTSSM L0 state (DEBUG0)

By reading the PCIe registers with a memory dump, the LTSSM in DEBUG0 stay at 0. I verify the registers one by one to check if the configuration has been correctly stored, it is appeared that the generation 2 and lane enable flag is not set in the PL_GEN2 register, and the force link seem to do nothing.

I have followed the TI documentation instruction, but I did not found my error. Also, I have tried with the PIPE loopback, but I had the same problem.

Regards William

  • 0
    TI__Guru* 81335 points

    Hi William,

    Thank you for the post.

    I have following suggestion to check at your end:

    1. You can run the "..\ti\pdk_keystone2_3_01_03_06\packages\exampleProjects\PCIE_K2LC66BiosExampleProject" PCIe example in root complex mode and compare the memory dump .

    2. Please refer the PCI FAQ from below link as well,

    Thank you.

  • 0
    TI__Mastermind 28085 points

    Hi,

    I have tested PCIe PHY loopback on C6678 EVM board, the same initialization steps are enough for K2L EVM. Please take a look at below similar e2e links.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points

    Hello,

    Thanks for the links.

    I resolved the problem, it was a wrong initialisation of the SerDes. I got the SerDes initialisation of the PCIe example provide in the MCSDK (CSL part), but I think I made a mystake here. Now, I take the initialisation provide in the second link, and it works.


    Regards William

  • 0 in reply to WilliamV
    TI__Mastermind 28085 points
    Thanks for your update.
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points
    Hello,

    I come back because I have an error with the PCIe generation. The generation 2 flag in the PL_GEN2 register cannot be set. Is there a specific register to configure in the SerDes configuration?

    Regards William
  • 0 in reply to WilliamV
    TI__Mastermind 28085 points

    Hi,

    Based on DIR_SPD bit field LTSSM to initiate a speed change to Gen2 after the link is initialized at Gen1 speed. For more information refer PCIe specification document.

    By-default DIR_SPD bit field set to 0 and LN_EN bit set to 1 on MCSDK PCIe example code. Refer below code to change the PL_GEN2 configuration.

    //BY-default MCSDK code
  /* Setting PL_GEN2 */   
  memset (&setRegs, 0, sizeof(setRegs));
  gen2.numFts = 0xF;
  gen2.dirSpd = 0x0;
  gen2.lnEn   = 1;
  setRegs.gen2 = &gen2;
  
//Change the PL_GEN2 configuration as below
  /* Setting PL_GEN2 */   
  memset (&setRegs, 0, sizeof(setRegs));
  gen2.numFts = 0xF;
  gen2.dirSpd = 0x1;
  gen2.lnEn   = 2;
  setRegs.gen2 = &gen2;

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points

    Hello,

    I already changed the DIR_SPD field in the PL_GEN2, but it doesn't change, it stays at 0.
    I use only one lane, so I keep the LN_EN = 1.

    Regards William

  • 0 in reply to WilliamV
    TI__Mastermind 28085 points
    Hi,

    I have validated PCIe Gen1 and Gen2 configuration on C6678 device. Your DSP side GEN2 configuration code is fine. Please try to confirm your End Point device(FPGA) will support GEN2 and it is configured as GEN2 mode.

    If FPGA run on GEN2 speed, Based on DIR_SPD bit field LTSSM to initiate a speed change to Gen2 after the link is initialized at Gen1 speed on DSP side.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points
    Hello,

    I am not on DSP, I work on ARM. I am currently in loopback mode, so I have nothing connected on the port.
    The loopback doesn't support the Gen 2?

    Regards William
  • 0 in reply to WilliamV
    TI__Mastermind 28085 points
    Hi,

    The C66xx PCI Express module supports PHY loopback in RC mode only.

    The PHY loopback is accomplished by switching the PHY to loopback where the transmitted data is looped back to the receive path at the PHY level. This mode can be used to perform TLP loopback even if there is no link partner. It is, however, possible to set up only when the PCIESS is used in RC mode. This limitation is because of the fact that link training cannot occur between two upstream ports; at least one port must
    be a downstream port.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 100 points
    Hello,

    I know the PHY loopback is limited to the RC mode, it's written in the PCIe documentation... I don't see the link with my question about the generation.
    Currently, I use only one lane. Do I need to configuration the lane 0 in RC, and the lane 1 in EP, in order to have a fully functional loopback?

    Regards William