AM3505AZERA GPMC Programming

Hello,

For our customers commercial video processor they are using an AM3505AZERA processor interfacing to Micron NAND flash (MT29F4G16ABADAH4:AIT:D). Thay have had a recent issue come to light where the flash is having bit flips occur after long periods of not being reprogrammed. This is found both in products that are running and products that are in storage. They have already explored the possibility of this being an ECC issue, and now they are entertaining the idea that our flash programming times are close enough to work but not long enough to fully charge cells.  The key engineer has investigated this a little bit and they are using the following values for GPMC initialization:

WRITE         GPMC_CONFIG1_0       0x00001800

WRITE         GPMC_CONFIG2_0       0x00080800

WRITE         GPMC_CONFIG3_0       0x00080800

WRITE         GPMC_CONFIG4_0       0x06000600

WRITE         GPMC_CONFIG5_0       0x00070808

WRITE         GPMC_CONFIG6_0       0x000003cf

WRITE         GPMC_CONFIG7_0       0x00000848

(^ default initializations for the AM3517EVM kit)

I have an issue with this because bits 12:8 of GPMC5 is the write cycle time as you can see above this is being programmed to 8 which at 600 Mhz is only 13.33 ns, the micron datasheet states a minimum 20ns.

I have done a considerable amount of browsing the e2e forums and app notes and programming guides provided by TI, I have also calculated what I think the timings should be, but I could be way off base. As this is pretty mission critical we are hestitant to make any changes without a “smoking gun”, however, our current reliability is unacceptable. I am hoping that there is a TI engineer who can help me get that smoking gun by providing the GPMC initialization values that are needed to be ONFI 1.0 compliant:

What would be even better is the actual register initializations.

To help things along I have attached the ONFI standard and the datasheet for the flash we are using.m60a_4gb_8gb_16gb_ecc_nand.pdfONFI_1_0_Standard.pdf