K2H14 - GEL INITIALIZATION

Hi,

Have you using TI provide .gel file for your testing? Have you referred the K2HEVM board for develop your custom board? TI provide K2H .gel file is directly support for EVM boards only. see the below .gel console log for K2H EVM

C66xx_0: GEL Output: 
Connecting Target...
C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.3 
C66xx_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000
C66xx_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (2b) PLLCTL = 0x00000048
C66xx_0: GEL Output: (2c) PLLCTL = 0x00000048
C66xx_0: GEL Output: (2d) Delay...
C66xx_0: GEL Output: (2e) SECCTL = 0x00810000
C66xx_0: GEL Output: (2f) PLLCTL = 0x0000004A
C66xx_0: GEL Output: (2g) Delay...
C66xx_0: GEL Output: (2h) PLLCTL = 0x00000048
C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000
C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (7) SECCTL = 0x00890000
C66xx_0: GEL Output: (8a) Delay...
C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
C66xx_0: GEL Output: (8d/e) Delay...
C66xx_0: GEL Output: (10) Delay...
C66xx_0: GEL Output: (12) Delay...
C66xx_0: GEL Output: (13) SECCTL = 0x00090000
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
C66xx_0: GEL Output: PLL has been configured (122.88 MHz * 16 / 1 / 2 = 983.04 MHz)
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... 
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL.
C66xx_0: GEL Output: Completed PA PLL Setup
C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0	 after: 0x0x07080400
C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040	 after: 0x0x00002040
C66xx_0: GEL Output: DDR begin
C66xx_0: GEL Output: XMC setup complete.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz.
C66xx_0: GEL Output: DDR3A initialization complete 
C66xx_0: GEL Output: DDR3 PLL Setup ... 
C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz.
C66xx_0: GEL Output: DDR3B initialization complete 
C66xx_0: GEL Output: DDR done

Have you set the Device Boot mode as NO-Boot mode?

Thanks,

Hello Sir,

I have set the Device boot mode as NO-BOOT. I am using CCS5.5V and I am loading the GEL file from the bellow location,

C:\ti\mcsdk_bios_3_00_03_15\tools\program_evm\gel. I Have choose the processor as 66AK2H12 in the target configuration

section.

Sir What can be the issue.

Regards,

Avinash N

Hi,

Your processor selection on target configuration and .gel file is fine.

I think problem on enabling the specific power domain on your custom board, please try to remove or uncommand the unwanted power up of modules on your .gel file to debug the issue.

Thanks,

Hello Sir,

I Have commented the PSC sections of All the other interfaced devices and try to access the DSP Section alone as shown bellow but still we are getting certain issues in accessing the register.

/**************************************************************************************************************************************************/

/*GEL SECTION*/

if (DNUM == 0)
    {
        GEL_TextOut( "Power on all PSC modules and DSP domains... \n");
    
        Set_PSC_State(PD1, LPSC_DEBUG, PSC_ENABLE);
        Set_PSC_State(PD7, LPSC_MSMCRAM, PSC_ENABLE);
        Set_PSC_State(PD8, LPSC_GEM_0, PSC_ENABLE);
        Set_PSC_State(PD9, LPSC_GEM_1, PSC_ENABLE);
        Set_PSC_State(PD10, LPSC_GEM_2, PSC_ENABLE);
        Set_PSC_State(PD11, LPSC_GEM_3, PSC_ENABLE);
        Set_PSC_State(PD12, LPSC_GEM_4, PSC_ENABLE);
        Set_PSC_State(PD13, LPSC_GEM_5, PSC_ENABLE);
        Set_PSC_State(PD14, LPSC_GEM_6, PSC_ENABLE);
        Set_PSC_State(PD15, LPSC_GEM_7, PSC_ENABLE);
        Set_PSC_State(PD16, LPSC_DDR3_0, PSC_ENABLE);
        Set_PSC_State(PD16, LPSC_DDR3_1, PSC_ENABLE);
        Set_PSC_State(PD31, LPSC_ARM, PSC_ENABLE);
   
        GEL_TextOut( "Power on all PSC modules and DSP domains... Done.\n" );
    }

/**************************************************************************************************************************************************/

/*ERROR SHOWN*/

C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.3
C66xx_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000
C66xx_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (2b) PLLCTL = 0x00000048
C66xx_0: GEL Output: (2c) PLLCTL = 0x00000048
C66xx_0: GEL Output: (2d) Delay...
C66xx_0: GEL Output: (2e) SECCTL = 0x00810000
C66xx_0: GEL Output: (2f) PLLCTL = 0x0000004A
C66xx_0: GEL Output: (2g) Delay...
C66xx_0: GEL Output: (2h) PLLCTL = 0x00000048
C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F
C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000
C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040
C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000
C66xx_0: GEL Output: (7) SECCTL = 0x00890000
C66xx_0: GEL Output: (8a) Delay...
C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002
C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004
C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000
C66xx_0: GEL Output: (8d/e) Delay...
C66xx_0: GEL Output: (10) Delay...
C66xx_0: GEL Output: (12) Delay...
C66xx_0: GEL Output: (13) SECCTL = 0x00090000
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (Delay...
C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT):
C66xx_0: GEL Output: PLL has been configured (122.88 MHz * 16 / 1 / 2 = 983.04 MHz)
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: Trouble Reading Memory Block at 0x2350814 on Page 0 of Length 0x4: (Error -1139 @ 0x2350814) Lost debug connection to device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)
C66xx_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x02350814     at (*(mdstat)&0x1f) [xtcievmk2x.gel:697]     at Set_PSC_State(1, 5, 0x3) [xtcievmk2x.gel:901]     at Set_Psc_All_On() [xtcievmk2x.gel:636]     at Global_Default_Setup_Silent() [xtcievmk2x.gel:565]     at OnTargetConnect() .
C66xx_0: Trouble Reading Register PC
C66xx_0: Trouble Reading Register ControlRegisters_CSR
C66xx_0: Trouble Reading Register ControlRegisters_CSR

/*************************************************************************************************************************************************************/

1. At the beginning of the gel file it prints as TCI6638K2K - What it actually means ?

2. Whether the GEL File is for TCI6638K2K  ?

3. Can i get the sample gel file for 66AK2H12 or 66AK2H14?

Regards,

Avinash N

Hi,

1. At the beginning of the gel file it prints as TCI6638K2K - What it actually means ?

TCI663xK2K and 66AK2Hxx devices are similar Multicore ARM + DSP Chip, TCI663xK2K devices additionally have Wireless Accelerators modules.

2. Whether the GEL File is for TCI6638K2K ?
3. Can i get the sample gel file for 66AK2H12 or 66AK2H14?

GEL file is common for both devices. MCSDK GEL file path: C:\ti\mcsdk_bios_3_01_03_06\tools\program_evm\gel\xtcievmk2x.gel

Thanks,

Hello Sir,

                 Can i get the Power Sleep Controller (PSC) Datasheet of keystone II Architecture.

                  In xtcievmk2x.gel around 30 power domain are configured. How to know about that in Detailed.

Regards,

Avinash N

Hello Sir,

                   We are Still Stuck up the same issue. Sir I required some answers.

Questions,

1. At No boot What will be the Boot mode configuration value?

2. Sir in the above screen till Core PLL we can able to access once when we are trying to access the PSC section after reading the DNUM we are getting the error  that,Reading Memory DNUM or the PSC Register ?

3. Sir whether Gel File we need to make any changes for the PSC ?

Can I Get the answer or solution as soon as possible.

Thanks in Advance.

Regards,

Avinash N

Hi,

Ans1: The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the associated boot process in software. Boot mode configuration value is 0 for No-boot mode.

Ans2: I will check with my team and get back to you.

Ans3: No.

Thanks,