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Does CORTEX-A15 core support SDIV/UDIV instructions by H/W?

Michi Yama
Guru 10030 points

Hi,

I have simple question regarding Cortex-A15 core of Keystone Multicore.

Does A15 core of Keystone multicore support Integer division instruction by hardware?

According to the ARMv7-A architecture reference manual, it is written in the below.

In an ARMv7-A implementation that does not include the Virtualization Extensions, the implementation of SDIV and
UDIV in both instruction sets is OPTIONAL, but the architecture permits an ARMv7-A implementation to not
implement SDIV and UDIV.

So I would like to know whether TI's A15 core support SDIV/UDIV or not.

Please advise me.

I appreciate your quick reply.

Best regards,

Michi 

  • 0
    TI__Guru* 81335 points

    Hi Michi,

    I have referred ARM Cortex-A15 MPCore Processor Technical Reference Manual (ARM) and it says it has support to SDIV/UDIV instructions by H/W.

    You can get the status by reading the "Instruction Set Attribute Register 0" ID_ISAR0 (Read-Only Reg) and reset value defined as 0x02101110.

    Thank you.