J5 -Eco: Bit clock and frame sync generation from MCLK confirmation code

Manju,

Let me start with McASP2. From what I understand (correct me if I am wrong) you need to get 12.288MHz from the AHCLKX_IN port and provide bit clock and frame sync to external audio codec:

12.288MHz -> AHCLKX_IN -> ACLKXCTL[4:0] CLKXDIV -> ACLKX pin -> bit clock -> audio codec
12.288MHz -> AHCLKX_IN -> ACLKXCTL[4:0] CLKXDIV -> XCLK -> AFSX pin -> frame sync -> audio codec

What frequency you need for the bit clock and frame sync? Do you need I2S mode?

BR
Pavel

Dear Pavel,

Ok, lets start with MCASP2.I need MCASP2 to provide clocks to codec as below:
12.288MHz -> AHCLKX_IN -> ACLKXCTL[4:0] CLKXDIV -> ACLKX pin -> bit clock -> audio codec
12.288MHz -> AHCLKX_IN -> ACLKXCTL[4:0] CLKXDIV -> XCLK -> AFSX pin -> frame sync -> audio codec

McAsp2 - 48Khz,16 bit ,2 Channels (I2S mode)

Manju,

These settings looks correct to me, but it will be better to verify these on the board:

1. Check ACLKX and AFSX pins, verify that clock is active, check that FS is 48KHz, bit clock is 1536KHz

2. Check the values of the below registers/bits before and after aplay command. After aplay should be:
CLKXM=1
HCLKXM=0
CLKXDIV=8

PFUNC[28] AFSX = 0, [27] AHCLKX = 0, [26] ACLKX = 0
PDIR[28] AFSX = 1, [27] AHCLKX = 0, [26] ACLKX = 1

BR
Pavel

Dear Pavel,

MCASP0 , MCASP2 and MCASP4 ports i tested the ACLKX and AFSX pins on custom board,

Below are results:

1. MCASP2 using "aplay –D hw:0,2 Test.wav"
   1. ACLKX is seen on oscilloscope.
   2. AFSX    is seen on oscilloscope.
   3. AXR0    is seen on oscilloscope.
      
      
2. MCASP0 using "aplay –D hw:0,0 Test.wav"
   1. ACLKX is not seen on oscilloscope
   2. AFSX is not seen on oscilloscope
   3. AXR0 is not seen on oscilloscope
   4. AXR1 is not seen on oscilloscope
3. MCASP4 using "aplay –D hw:0,1 Test.wav"
   1. ACLKX is not seen on oscilloscope
   2. AFSX is not seen on oscilloscope
   3. AXR0 is not seen on oscilloscope

I'm attaching the source files for verification:

4530.devices.c7610.davinci-mcasp.h5238.davinci-mcasp.c3681.davinci-evm.c5226.clock814x_data.c4213.board-ti811xevm.c

Manju,

Can you provide me the below registers values, you can check these with devmem2 tool:

PINCNTL16/0x4814089C
PINCNTL39/0x48140898
PINCNTL40/0x4814089C
PINCNTL41/0x481408A0
PINCNTL42/0x481408A4

PINCNTL14/0x48140834
PINCNTL17/0x48140840
PINCNTL18/0x48140844
PINCNTL21/0x48140850
PINCNTL22/0x48140854

MCASP_AHCLK_CLKSRC/0x481C52D4
CM_AUDIOCLK_MCASP2_CLKSEL/0x48180384
CM_AUDIOCLK_MCASP0_CLKSEL/0x4818037C
CM_ALWON_MCASP2_CLKCTRL/0x48181548
CM_ALWON_MCASP0_CLKCTRL/0x48181540

BR
Pavel

Dear Pavel,
Below are values:


PINCNTL16/0x4814089C 0x000E0001

PINCNTL39/0x48140898 0x00060001

PINCNTL40/0x4814089C 0x000E0001

PINCNTL41/0x481408A0 0x000E0001

PINCNTL42/0x481408A4 0x000E0001



PINCNTL14/0x48140834 0x000C0001

PINCNTL17/0x48140840 0x00040001

PINCNTL18/0x48140844 0x000C0001

PINCNTL21/0x48140850 0x000C0001

PINCNTL22/0x48140854 0x000E0001



MCASP_AHCLK_CLKSRC/0x481C52D4 0x00000000

CM_AUDIOCLK_MCASP2_CLKSEL/0x48180384 0x00000002

CM_AUDIOCLK_MCASP0_CLKSEL/0x4818037C 0x00000000

CM_ALWON_MCASP2_CLKCTRL/0x48181548 0x00000002

CM_ALWON_MCASP0_CLKCTRL/0x48181540 0x00000002

Manju,

The above settings looks correct to me.

Make sure you are not using McASP0 in DIT mode, where it is possible to use only internally generated AHCLKX. Can you config McASP0 in I2S 16-bit mode (same as the working McASP2), will McASP0 work then?

Can you provide me the value of the below registers (after executing aplay command), you can get these registers values with devmem2:

MCASP0.PFUNC/0x48038010
MCASP0.PDIR/0x48038014
MCASP0.PDIN/0x4803801C
MCASP0.GBLCTL/0x48038044
MCASP0.XGBLCTL/0x480380A0
MCASP0.XMASK/0x480380A4
MCASP0.XFMT/0x480380A8
MCASP0.AFSXCTL/0x480380AC
MCASP0.ACLKXCTL/0x480380B0
MCASP0.AHCLKXCTL/0x480380B4
MCASP0.XTDM/0x480380B8
MCASP0.XINTCTL/0x480380BC
MCASP0.XSTAT/0x480380C0
MCASP0.XSLOT/0x480380C4
MCASP0.XCLKCHK/0x480380C8
MCASP0.SRCTL0/0x48038180
MCASP0.SRCTL1/0x48038184
MCASP0.XBUF0/0x48038200
MCASP0.XBUF1/0x48038204



MCASP2.PFUNC/0x48050010
MCASP2.PDIR/0x48050014
MCASP2.PDIN/0x4805001C
MCASP2.GBLCTL/0x48050044
MCASP2.XGBLCTL/0x480500A0
MCASP2.XMASK/0x480500A4
MCASP2.XFMT/0x480500A8
MCASP2.AFSXCTL/0x480500AC
MCASP2.ACLKXCTL/0x480500B0
MCASP2.AHCLKXCTL/0x480500B4
MCASP2.XTDM/0x480500B8
MCASP2.XINTCTL/0x480500BC
MCASP2.XSTAT/0x480500C0
MCASP2.XSLOT/0x480500C4
MCASP2.XCLKCHK/0x480500C8
MCASP2.SRCTL0/0x48050180
MCASP2.SRCTL1/0x48050184
MCASP2.XBUF0/0x48050200
MCASP2.XBUF1/0x48050204


BR
Pavel

Dear Pavel,

Values:

MCASP0.PFUNC/0x48038010 0x00000000

MCASP0.PDIR/0x48038014 0x00000000

MCASP0.PDIN/0x4803801C 0x00000006

MCASP0.GBLCTL/0x48038044 0x00000000

MCASP0.XGBLCTL/0x480380A0 0x00000000

MCASP0.XMASK/0x480380A4 0x00000000

MCASP0.XFMT/0x480380A8 0x00000000

MCASP0.AFSXCTL/0x480380AC 0x00000000

MCASP0.ACLKXCTL/0x480380B0 0x00000060

MCASP0.AHCLKXCTL/0x480380B4 0x00008000

MCASP0.XTDM/0x480380B8 0x00000000

MCASP0.XINTCTL/0x480380BC 0x00000000

MCASP0.XSTAT/0x480380C0 0x0000010C

MCASP0.XSLOT/0x480380C4 0x0000017F

MCASP0.XCLKCHK/0x480380C8 0x00000000

MCASP0.SRCTL0/0x48038180 0x00000000

MCASP0.SRCTL1/0x48038184 0x00000000

MCASP0.XBUF0/0x48038200 0x00000000

MCASP0.XBUF1/0x48038204 0x00000000



MCASP2.PFUNC/0x48050010 0x00000000

MCASP2.PDIR/0x48050014 0x00000000

MCASP2.PDIN/0x4805001C 0x14000003

MCASP2.GBLCTL/0x48050044 0x00000000

MCASP2.XGBLCTL/0x480500A0 0x00000000

MCASP2.XMASK/0x480500A4 0x00000000

MCASP2.XFMT/0x480500A8 0x00000000

MCASP2.AFSXCTL/0x480500AC 0x00000000


MCASP2.ACLKXCTL/0x480500B0 0x00000060

MCASP2.AHCLKXCTL/0x480500B4 0x00008000

MCASP2.XTDM/0x480500B8 0x00000000

MCASP2.XINTCTL/0x480500BC 0x00000000

MCASP2.XSTAT/0x480500C0 0x0000010C

MCASP2.XSLOT/0x480500C4 0x0000017F

MCASP2.XCLKCHK/0x480500C8 0x00000000

MCASP2.SRCTL0/0x48050180 0x00000000

MCASP2.SRCTL1/0x48050184 0x00000000

MCASP2.XBUF0/0x48050200 0x00000000

MCASP2.XBUF1/0x48050204 0x00000000


Where i need to modify to configure for 16-bit Mode for I2S , I have made tdm_slots=2, will this configure to 16-bit? Below is my code chunk:


static struct snd_platform_data ti811x_evm_snd_data[] = {

{
.tx_dma_offset = 0x46000000,
.rx_dma_offset = 0x46000000,
.op_mode = DAVINCI_MCASP_IIS_MODE,
.num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp0),-------------------------------------MCASP0
.tdm_slots = 2,
.serial_dir = ti811x_iis_serializer_direction_mcasp0,
.asp_chan_q = EVENTQ_2,
.version = MCASP_VERSION_2,
.txnumevt = 1,
.rxnumevt = 1,
.clk_input_pin = MCASP_AHCLKX_IN,
},

{
.tx_dma_offset = 0x4A1AB000,
.rx_dma_offset = 0x4A1AB000,
.op_mode = DAVINCI_MCASP_IIS_MODE,
.num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp4),-----------------------------------------MCASP4
.tdm_slots = 8,
.serial_dir = ti811x_iis_serializer_direction_mcasp4,
.asp_chan_q = EVENTQ_2,
.version = MCASP_VERSION_2,
.txnumevt = 1,
.rxnumevt = 1,
.clk_input_pin = MCASP_AHCLKX_IN,
},

{
.tx_dma_offset = 0x46800000,
.rx_dma_offset = 0x46800000,
.op_mode = DAVINCI_MCASP_IIS_MODE,
.num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp2),---------------------------------------MCASP2
.tdm_slots = 2,
.serial_dir = ti811x_iis_serializer_direction_mcasp2,
.asp_chan_q = EVENTQ_2,
.version = MCASP_VERSION_2,
.txnumevt = 1,
.rxnumevt = 1,
/* McASP2_AHCLKX out to feed CODEC CLK*/
.clk_input_pin = MCASP_AHCLKX_IN,
}
};


static u8 ti811x_iis_serializer_direction_mcasp2[] = {
TX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
};

static u8 ti811x_iis_serializer_direction_mcasp0[] = {
RX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
};

static u8 ti811x_iis_serializer_direction_mcasp4[] = {
TX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
};

static int evm_hw_tdm_mcasp4_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret = 0;
unsigned sysclk;

sysclk = 12288000;

/* set codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;

/* set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT);
if (ret < 0)
return ret;


ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 4);
if (ret < 0)
return ret;


return 0;
}

static int evm_hw_i2s_mcasp0_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret = 0;
unsigned sysclk;

sysclk = 12288000;

/* set codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT_I2S_CODEC);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;

/* set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT_I2S);
if (ret < 0)
return ret;


ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 4);
if (ret < 0)
return ret;


return 0;
}

static int evm_hw_i2s_mcasp2_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
int ret = 0;
unsigned sysclk;

sysclk = 12288000;

/* set codec DAI configuration */
ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT_I2S_CODEC);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_IN);
if (ret < 0)
return ret;

/* set cpu DAI configuration */
ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT_I2S);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT);
if (ret < 0)
return ret;

ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 4);
if (ret < 0)
return ret;

return 0;
}

Manju,

Is this issue (no signals on MCASP0 AFSX/ACLKX) observed in the J5Eco EVM or in your custom board?

Can you check if your flow enters in the below case?

davinci-mcasp.c

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)

{

switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {

case SND_SOC_DAIFMT_CBS_CFS:

/* codec is clock and frame slave */

mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);

mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);

mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));

break;

...

}

I am asking this, as I see your PDIR reg is 0x00000000, not 0x1C000000

BR
Pavel

Dear Pavel,

I have enabled MCASP0 MCASP2 an MCASP4.

MCASP2 ACLKX , AFSX and ARX0 is seen on oscilloscope after using aplay command.

But MCASP0 and MCASP4 no output on any pins using aplay commands.

No its not entering below function and case.I added printk messages in

davinci-mcasp.c

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)

{

printk("MCASP Port Format Configuration begins.....\n");

switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {

case SND_SOC_DAIFMT_CBS_CFS:

/* codec is clock and frame slave */

mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);

mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);

mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));

printk("MCASP Port.%d as master\n",i);

break;

...

}

Is this issue (no signals on MCASP0 AFSX/ACLKX) observed in the J5Eco EVM or in your custom board?

manju gunnaiah said:

No its not entering below function and case.

Can you check way. Your flow should go into this case to set ACLKX and AFSX as outputs. Your flow should go into this case, right after aplay command is executed.

BR

Can you also remove the below line of code:

davinci-mcasp.c

static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)

{

if (stream == SNDRV_PCM_STREAM_PLAYBACK) {

/* bit stream is MSB first  with no delay */

/* DSP_B mode */

mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);

....

}

This line of code sets bit AHCLKXCTL[15] HCLKXM to 1, and this is not what we need.

BR
Pavel

Dear Pavel,

I will remove and update you.

Dear Pavel,

Below is the output,

root@c6a811x-evm:/bin/audiosamples# aplay -D "hw:0,2" LRMonoPhase4.wav --------------MCASP2
Playing WAVE 'LRMCASP Port Format Configuration begins.....
MonoPhase4.wav' MCASP Port as SND_SOC_DAIFMT_CBS_CFS
: Signed 16 bit MCASP Port as SND_SOC_DAIFMT_NB_IF
Little Endian, Rate 48000 Hz, Stereo
underrun!!! (at least 0.174 ms long)
underrun!!! (at least 0.044 ms long)

root@c6a811x-evm:/bin/audiosamples# aplay -D "hw:0,0" LRMonoPhase4.wav --------------------MCASP0
Playing WAVE 'LRMCASP Port Format Configuration begins.....
MonoPhase4.wav' MCASP Port as SND_SOC_DAIFMT_CBS_CFS
: Signed 16 bit MCASP Port as SND_SOC_DAIFMT_NB_IF
Little Endian, Rate 48000 Hz, Stereo
aplay: pcm_write:1694: write error: Input/output error


root@c6a811x-evm:/bin/audiosamples# aplay -D "hw:0,1" LRMonoPhase4.wav -----------------------MCASP4
Playing WAVE 'LRMonoPhase4.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
MCASP Port Format Configuration begins.....
MCASP Port as SND_SOC_DAIFMT_CBS_CFS
MCASP Port as SND_SOC_DAIFMT_IB_NF
aplay: pcm_write:1694: write error: Input/output error

Is this issue (no signals on MCASP0 AFSX/ACLKX) observed in the J5Eco EVM or in your custom board?

Do you now see signals on AFSX/ACLKX?

BR
Pavel

Dear Pavel,

This issue is same on J5Eco EVM board too.

Manju,

Can you also update the below line of code:

davinci-mcasp.c

case SND_SOC_DAIFMT_CBS_CFS:

mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 0x5 << 26));

Update me with the result.

BR
Pavel

Dear Pavel,

Now MCASP0 and MCASP2 clocks are seen on Oscilloscope.

With new custom boards AUDIO_CLKIN0=50Mhz.

Data i can see on oscilloscope from MCASP2 since AXR[0] is configured as transmitter.No data from MCASP0 since AXR[0] and AXR[1] is configured as receiver in serializer.

static u8 ti811x_iis_serializer_direction_mcasp2[] = {
    TX_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,---------------------------MCA2_AXR0
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
};

static u8 ti811x_iis_serializer_direction_mcasp0[] = {
    RX_MODE,    RX_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,--------------------------------MCA0_AXR0 and MCA0_AXR1
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
};

static u8 ti811x_iis_serializer_direction_mcasp4[] = {
    TX_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,--------------------------------------------MCA4_AXR0
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
};

static struct snd_platform_data ti811x_rsb_snd_data[] = {
    {
     .tx_dma_offset  = 0x46000000,
         .rx_dma_offset  = 0x46000000,
         .op_mode        = DAVINCI_MCASP_IIS_MODE,
         .num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp0),
         .tdm_slots      = 2,
         .serial_dir     = ti811x_iis_serializer_direction_mcasp0,
         .asp_chan_q     = EVENTQ_2,
         .version        = MCASP_VERSION_2,
         .txnumevt    = 1,
     .rxnumevt    = 1,
     .clk_input_pin    = MCASP_AHCLKX_IN,
    },

    {
    .tx_dma_offset    = 0x4A1AB000,
    .rx_dma_offset    = 0x4A1AB000,
    .op_mode    = DAVINCI_MCASP_IIS_MODE,
    .num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp4),
    .tdm_slots    = 4,
    .serial_dir    = ti811x_iis_serializer_direction_mcasp4,
    .asp_chan_q    = EVENTQ_2,
    .version    = MCASP_VERSION_2,
    .txnumevt    = 1,
    .rxnumevt    = 1,
    .clk_input_pin    = MCASP_AHCLKX_IN,
    },

    {
    .tx_dma_offset    = 0x46800000,
    .rx_dma_offset    = 0x46800000,
    .op_mode    = DAVINCI_MCASP_IIS_MODE,
    .num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp2),
    .tdm_slots    = 2,
    .serial_dir    = ti811x_iis_serializer_direction_mcasp2,
    .asp_chan_q    = EVENTQ_2,
    .version    = MCASP_VERSION_2,
    .txnumevt    = 1,
    .rxnumevt    = 1,
    /* McASP2_AHCLKX out to feed CODEC CLK*/
    .clk_input_pin    = MCASP_AHCLKX_IN,
    },
};

root@c6a811x-evm:/bin/audiosamples# aplay -D "hw:0,2" LRMonoPhase4.wav ----------------------------------------------MCASP2
Playing WAVE 'LRMCASP Port Format setting begins
MonoPhase4.wav' MCASP SND_SOC_DAIFMT_CBS_CFS
: Signed 16 bit MCASP SND_SOC_DAIFMT_NB_IF
Little Endian, Rate 48000 Hz, Stereo

root@c6a811x-evm:/bin/audiosamples# aplay -D "hw:0,0" LRMonoPhase4.wav --------------------------------------------------------MCASP0
Playing WAVE 'LRMonoPhase4.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
MCASP Port Format setting begins
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/bin/audiosamples# aplay -D "hw:0,1" LRMonoPhase4.wav --------------------------------------------------------MCASP4
Playing WAVE 'LRMCASP Port Format setting begins
MonoPhase4.wav' MCASP SND_SOC_DAIFMT_CBS_CFS
: Signed 16 bit MCASP SND_SOC_DAIFMT_IB_NF
Little Endian, Rate 48000 Hz, Stereo
aplay: pcm_write:1694: write error: Input/output error

Dear Pavel,

But MCASP4 clocks never shows up.Only MCASP0 and MCASP2 clocks are seen.

MCASP4 No clock in below image:

MCASP0 clocks:

MCASP2 clocks:

#define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF)

#define AUDIO_FORMAT_I2S (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_IF)

#define AUDIO_FORMAT_I2S_CODEC (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_NF)


static int evm_hw_tdm_mcasp4_params(struct snd_pcm_substream *substream,
             struct snd_pcm_hw_params *params)
{
    struct snd_soc_pcm_runtime *rtd = substream->private_data;
    struct snd_soc_dai *codec_dai = rtd->codec_dai;
    struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
    int ret = 0;
    unsigned sysclk;
    
        //sysclk = 12288000;
          sysclk = 50000000;
    
    /* set codec DAI configuration */
    ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT);
    if (ret < 0)
        return ret;    
    
    ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_IN);
    if (ret < 0)
        return ret;    
    
    /* set cpu DAI configuration */
    ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT);
    if (ret < 0)
        return ret;

    
    ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT);
    if (ret < 0)
        return ret;
    
    //ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 2);
    ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 8);
    if (ret < 0)
        return ret;
    

    return 0;
}

static int evm_hw_i2s_mcasp0_params(struct snd_pcm_substream *substream,
             struct snd_pcm_hw_params *params)
{
    struct snd_soc_pcm_runtime *rtd = substream->private_data;
    struct snd_soc_dai *codec_dai = rtd->codec_dai;
    struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
    int ret = 0;
    unsigned sysclk;
    
        //sysclk = 12288000;
          sysclk = 50000000;

    /* set codec DAI configuration */
    ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT_I2S_CODEC);
    if (ret < 0)
        return ret;    
    
    ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_IN);
    if (ret < 0)
        return ret;

    /* set cpu DAI configuration */
    ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT_I2S);
    if (ret < 0)
        return ret;
    
    
    ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT);
    if (ret < 0)
        return ret;
    
    //ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 5);
    ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 22);
    if (ret < 0)
        return ret;
    

    return 0;
}

static int evm_hw_i2s_mcasp2_params(struct snd_pcm_substream *substream,
             struct snd_pcm_hw_params *params)
{
    struct snd_soc_pcm_runtime *rtd = substream->private_data;
    struct snd_soc_dai *codec_dai = rtd->codec_dai;
    struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
    int ret = 0;
    unsigned sysclk;
    
        //sysclk = 12288000;
            sysclk = 50000000;

    /* set codec DAI configuration */
    ret = snd_soc_dai_set_fmt(codec_dai, AUDIO_FORMAT_I2S_CODEC);
    if (ret < 0)
        return ret;    
    
    ret = snd_soc_dai_set_sysclk(codec_dai, 0, sysclk, SND_SOC_CLOCK_IN);
    if (ret < 0)
        return ret;

    /* set cpu DAI configuration */
    ret = snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT_I2S);
    if (ret < 0)
        return ret;
    
    ret = snd_soc_dai_set_sysclk(cpu_dai, 0, sysclk, SND_SOC_CLOCK_OUT);
    if (ret < 0)
        return ret;
    
    //ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 8);
    ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, 33);
    if (ret < 0)
        return ret;

    return 0;
}

#if 0
static int evm_spdif_hw_params(struct snd_pcm_substream *substream,
                struct snd_pcm_hw_params *params)
{
    struct snd_soc_pcm_runtime *rtd = substream->private_data;
    struct snd_soc_dai *cpu_dai = rtd->cpu_dai;

    /* set cpu DAI configuration */
    return snd_soc_dai_set_fmt(cpu_dai, AUDIO_FORMAT);
}


static struct snd_soc_ops evm_spdif_ops = {
    .hw_params = evm_spdif_hw_params,
};

#endif
static struct snd_soc_ops evm_tdm_mcasp4_ops = {
    .hw_params = evm_hw_tdm_mcasp4_params,
};

static struct snd_soc_ops evm_i2s_mcasp0_ops = {
    .hw_params = evm_hw_i2s_mcasp0_params,
};

static struct snd_soc_ops evm_i2s_mcasp2_ops = {
    .hw_params = evm_hw_i2s_mcasp2_params,
};

Manju,

From what I understand, we will focus on McASP4 now.

Can you provide me the output of the below command:

# aplay -l

Can you provide me the below registers values, you can get these with devmem2:

MCA[4]_ACLKX/PINCNTL51/0x481408C8
MCA[4]_AFSX/PINCNTL52/0x481408CC
MCA[4]_AHCLKX/PINCNTL15/0x48140838
MCA[4]_AXR[0]/PINCNTL53/0x481408D0

CM_ALWON_MCASP_3_4_5_CLKCTRL/0x4818156C

BR
Pavel

Dear Pavel,

Below are the details:

root@c6a811x-evm:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 1: AIC3X tlv320aic3x-hifi-1 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 2: AIC3X tlv320aic3x-hifi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0

MCA[4]_ACLKX/PINCNTL51/0x481408C8 0x00000001

MCA[4]_AFSX/PINCNTL52/0x481408CC 0x00000001

MCA[4]_AHCLKX/PINCNTL15/0x48140838 0x000C0001

MCA[4]_AXR[0]/PINCNTL53/0x481408D0 0x00000001

CM_ALWON_MCASP_3_4_5_CLKCTRL/0x4818156C 0x00000002

manju gunnaiah said:

MCA[4]_AFSX/PINCNTL52/0x481408CC 0x00000001

manju gunnaiah said:

MCA[4]_AXR[0]/PINCNTL53/0x481408D0 0x00000001

Can you set bit 19 to 1, we need to keep the reset value, you should have 0x00080001 in PINCNTL52 and PINCNTL53

manju gunnaiah said:

MCA[4]_AHCLKX/PINCNTL15/0x48140838 0x000C0001

Can you provide me also the values of the below registers:

MCA[0]_AHCLKX/PINCNTL14/0x48140834

MCA[2]_AHCLKX/PINCNTL16/0x4814083C


BR
Pavel

Dear Pavel,

Can you set bit 19 to 1, we need to keep the reset value, you should have 0x00080001 in PINCNTL52 and PINCNTL53

Where i need to modify In order to set bit 19 to 1 ?

Below are the details:

MCA[0]_AHCLKX/PINCNTL14/0x48140834    0x000C0001

MCA[2]_AHCLKX/PINCNTL16/0x4814083C     0x000C0001

manju gunnaiah said:

Where i need to modify In order to set bit 19 to 1 ?

Refer to:

processors.wiki.ti.com/.../TI811X_PSP_User_Guide

Dear Pavel,
Still value is same after setting also

MCA[4]_AFSX/PINCNTL52/0x481408CC 0x00000001

MCA[4]_AXR[0]/PINCNTL53/0x481408D0 0x00000001

omap_mux_init_signal("xref_clk0.xref_clk0", 0);
//Modified to enable MCASP 0,2,4
omap_mux_init_signal("mcasp0_aclkx_ti811x.mcasp0_aclkx_ti811x", 0);
omap_mux_init_signal("mcasp0_fsx_ti811x.mcasp0_fsx_ti811x", 0);
omap_mux_init_signal("mcasp0_axr0_ti811x.mcasp0_axr0_ti811x",0);
omap_mux_init_signal("mcasp0_axr1_ti811x.mcasp0_axr1_ti811x",0);


omap_mux_init_signal("mcasp2_aclkx_ti811x.mcasp2_aclkx_ti811x", 0);
omap_mux_init_signal("mcasp2_fsx_ti811x.mcasp2_fsx_ti811x",0);
omap_mux_init_signal("mcasp2_axr0_ti811x.mcasp2_axr0_ti811x",0);
omap_mux_init_signal("mcasp2_axr1_ti811x.mcasp2_axr1_ti811x", 0);

omap_mux_init_signal("mcasp4_aclkx_ti811x.mcasp4_aclkx_ti811x",0);
omap_mux_init_signal("mcasp4_fsx_ti811x.mcasp4_fsx_ti811x",0);
omap_mux_init_signal("mcasp4_axr0_ti811x.mcasp4_axr0_ti811x",0);

Dear Pavel,

MCASP4 is still not showing clock.

 

manju gunnaiah said:

omap_mux_init_signal("mcasp4_fsx_ti811x.mcasp4_fsx_ti811x",0);
omap_mux_init_signal("mcasp4_axr0_ti811x.mcasp4_axr0_ti811x",0);

Can you try the below modification:

omap_mux_init_signal("mcasp4_fsx_ti811x.mcasp4_fsx_ti811x",0 | TI814X_SLEW_SLOW);
omap_mux_init_signal("mcasp4_axr0_ti811x.mcasp4_axr0_ti811x",0 | TI814X_SLEW_SLOW);

BR
Pavel

Dear Pavel,
I have added below lines:

omap_mux_init_signal("mcasp4_aclkx_ti811x.mcasp4_aclkx_ti811x", 0 | TI814X_SLEW_SLOW);------0x00080001
omap_mux_init_signal("mcasp4_fsx_ti811x.mcasp4_fsx_ti811x", 0 | TI814X_SLEW_SLOW);------0x00080001
omap_mux_init_signal("mcasp4_axr0_ti811x.mcasp4_axr0_ti811x", 0 | TI814X_SLEW_SLOW);------0x00080001

But still no clock output on MCASP4 ports.

Manju,

manju gunnaiah said:

omap_mux_init_signal("mcasp4_aclkx_ti811x.mcasp4_aclkx_ti811x", 0 | TI814X_SLEW_SLOW);------0x00080001

I am afraid you misunderstand my directions. Please check careful my previous posts, you will find that I have never requested from you to modify the MCA[4]_ACLKX/PINCNTL51/0x481408C8 value.

If you do not agree, please find and share in which post exactly I have requested to you to change MCA[4]_ACLKX/PINCNTL51/0x481408C8 from 0x00000001 to 0x00080001?

BR
Pavel

Dear Pavel,

Sorry, i misinterpreted your direction, i thought same thing holds good for MCA[4]_ACLKX/PINCNTL51/0x481408C8.

I modified MCA[4]_ACLKX/PINCNTL51/0x481408C8 back to same.

But again no clocks on MCASP4 port.

manju gunnaiah said:

omap_mux_init_signal("mcasp4_fsx_ti811x.mcasp4_fsx_ti811x", 0 | TI814X_SLEW_SLOW);------0x00080001
omap_mux_init_signal("mcasp4_axr0_ti811x.mcasp4_axr0_ti811x", 0 | TI814X_SLEW_SLOW);------0x00080001

Do you have the value of 0x00080001 when checking with devmem2 FSX and AXR0?

BR
Pavel

Can you also share the latest version of your linux-kernel/arch/arm/plat-omap/include/plat/asp.h file

Can you also check that your flow goes through the below if:

devices.c

else if(id==1)
{
if (machine_is_ti8168evm() || machine_is_ti8148evm()
|| machine_is_ti811xevm()) {
ti81xx_mcasp4_device.id = 4;
ti81xx_mcasp4_device.resource = ti81xx_mcasp4_resource;
ti81xx_mcasp4_device.num_resources = ARRAY_SIZE(ti81xx_mcasp4_resource);
}

Dear Pavel,

Yes , i have  have the value of 0x00080001 when checking with devmem2 FSX and AXR0.

root@c6a811x-evm:/home/PCM# devmem2 0x481408CC
/dev/mem opened.
Memory mapped at address 0x401a9000.
Read at address  0x481408CC (0x401a98cc): 0x00080001
root@c6a811x-evm:/home/PCM# devmem2 0x481408D0
/dev/mem opened.
Memory mapped at address 0x40282000.
Read at address  0x481408D0 (0x402828d0): 0x00080001

7635.asp.h

Dear Pavel,

It is entering into devices.c

else if(id==1)

{

if (machine_is_ti8168evm() || machine_is_ti8148evm()

|| machine_is_ti811xevm()) {

ti81xx_mcasp4_device.id = 4;

ti81xx_mcasp4_device.resource = ti81xx_mcasp4_resource;

ti81xx_mcasp4_device.num_resources = ARRAY_SIZE(ti81xx_mcasp4_resource);

printk("Registering MCASP4 from ti81xx_register_mcasp function...\n");

}

root@c6a811x-evm:~# dmesg|grep -inr Mcasp
38:MCASP0 AHCLKX clk_get successed.
39:MCASP2 AHCLKX clk_get successed.
40:MCASP4 AHCLKX clk_get successed.
42:MCASP0 parent clock setting successed.
43:MCASP2 parent clock setting successed.
44:MCASP4 parent clock setting successed.
111:Registering MCASP0 from ti81xx_register_mcasp function...
112:PM: Adding info for platform:davinci-mcasp.0
113:Registering MCASP4 from ti81xx_register_mcasp function...
114:PM: Adding info for platform:davinci-mcasp.4
115:Registering MCASP2 from ti81xx_register_mcasp function...
116:PM: Adding info for platform:davinci-mcasp.2
509:PM: Adding info for No Bus:DIRANA3_MCASP0
510:asoc: tlv320aic3x-hifi <-> davinci-mcasp.0 mapping ok
511:PM: Adding info for No Bus:AMPLIFIER_MCASP4
512:asoc: tlv320aic3x-hifi <-> davinci-mcasp.4 mapping ok
513:PM: Adding info for No Bus:DIRANA3_MCASP2
514:asoc: tlv320aic3x-hifi <-> davinci-mcasp.2 mapping ok

You can see clock on MCA[0]_ACLKX/AE5 and MCA[2]_ACLKX/AE10 pins, but you can not see clock on MCA[4]_ACLKX/AE3, right?


Can you provide me the value of the below registers (after executing aplay command), you can get these registers values with devmem2:

MCASP0.PFUNC/0x48038010
MCASP0.PDIR/0x48038014
MCASP0.PDIN/0x4803801C

MCASP2.PFUNC/0x48050010
MCASP2.PDIR/0x48050014
MCASP2.PDIN/0x4805001C

MCASP4.PFUNC/0x4A1A8010
MCASP4.PDIR/0x4A1A8014
MCASP4.PDIN/0x4A1A801C

BR
Pavel

Dear Pavel,

Please find below details:

MCASP0.PFUNC/0x48038010 0x00000000

MCASP0.PDIR/0x48038014 0x00000000

MCASP0.PDIN/0x4803801C 0x00000004



MCASP2.PFUNC/0x48050010 0x00000000

MCASP2.PDIR/0x48050014 0x00000000

MCASP2.PDIN/0x4805001C 0x00000000



MCASP4.PFUNC/0x4A1A8010 0x00000000

MCASP4.PDIR/0x4A1A8014 0x00000000

MCASP4.PDIN/0x4A1A801C 0x00000008

Manju,

Are you sure you are getting these values after running the aplay command?

BR
Pavel

Dear Pavel,

Yes I can see clock on MCA[0]_ACLKX/AE5 and MCA[2]_ACLKX/AE10 pins, but can not see clock on MCA[4]_ACLKX/AE3.

I'm getting these values before running aplay command.

Below are values after running aplay commands:

MCASP0.PFUNC/0x48038010 0x00000000

MCASP0.PDIR/0x48038014 0x1C000000

MCASP0.PDIN/0x4803801C 0x00000004



MCASP2.PFUNC/0x48050010 0x00000000

MCASP2.PDIR/0x48050014 0x1C000001

MCASP2.PDIN/0x4805001C 0x10000000



MCASP4.PFUNC/0x4A1A8010 0x00000000

MCASP4.PDIR/0x4A1A8014 0x1C000001

MCASP4.PDIN/0x4A1A801C 0x00000008

Dear Pavel, 

I have attached all register value dump for MCASP0 MCASP2 and MCASP4 before aplay command and after aplay command6644.MCASP_REGISTER_DUMPS.xlsx. Please find the below attachment.

manju gunnaiah said:

Below are values after running aplay commands:

manju gunnaiah said:

MCASP0.PDIR/0x48038014 0x1C000000

manju gunnaiah said:

MCASP2.PDIR/0x48050014 0x1C000001

manju gunnaiah said:

MCASP4.PDIR/0x4A1A8014 0x1C000001

Can you also update the below line of code:

davinci-mcasp.c

case SND_SOC_DAIFMT_CBS_CFS:

mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 0x5 << 26));

Update me with the result.

BR
Pavel

0523.davinci-mcasp.cDear Pavel,

Those values are after running aplay command.

You have already suggested in earlier post to modify above change.I have added the same change and didn't got MCASP4 clocks.

case SND_SOC_DAIFMT_CBS_CFS:

/* codec is clock and frame slave */

mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);

mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);

mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

/*mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));*/

mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x5 << 26));//Pavel modification applied

printk("MCASP SND_SOC_DAIFMT_CBS_CFS\n");

break;

Manju,

Can you put print statements of the McASP4 PDIR register before and after the mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x5 << 26)); line?

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
                     unsigned int fmt)
{
    struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
    void __iomem *base = dev->base;

    static void __iomem *mcasp4_base;

   mcasp4_base = ioremap(0x4A1A8000, SZ_4K);

printk("MCASP Port Format setting begins\n");
    switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
    case SND_SOC_DAIFMT_CBS_CFS:
        /* codec is clock and frame slave */
        mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
        mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

        mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
        mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);

        /*mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));*/

printk("McASP4.PDIR = %x\n",__raw_readl(mcasp4_base + 0x14);

mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x5 << 26));//Pavel modification applied-Manju.g

printk("McASP4.PDIR = %x\n",__raw_readl(mcasp4_base + 0x14);

printk("MCASP SND_SOC_DAIFMT_CBS_CFS\n");
        break;

Update me with the result.

BR
Pavel

Dear Pavel,

Please find the output of above changes:

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra

w

Playing raw dataMCASP Port Format setting begins

'04Track.raw' :Before writing McASP4.PDIR = 0

Signed 16 bit LAfter writing McASP4.PDIR = 14000000

ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS

te 48000 Hz, SteMCASP SND_SOC_DAIFMT_IB_NF

reo

aplay: pcm_write:1694: write error: Input/output error

manju gunnaiah said:

Signed 16 bit LAfter writing McASP4.PDIR = 14000000

This looks correct. Can you double check that you have 0x1C000000 value in McASP4.PDIR with devmem2 after running the aplay?

BR
Pavel

Dear Pavel,

Below is the result.It shows initial aplay sets right value.Later aplay's value is altered.

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 0
 Signed 16 bit LAfter writing McASP4.PDIR = 14000000
ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS
te 48000 Hz, SteMCASP SND_SOC_DAIFMT_IB_NF
reo
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# devmem2 0x4a1a8014
/dev/mem opened.
Memory mapped at address 0x400bd000.
Read at address  0x4A1A8014 (0x400bd014): 0x1C000001

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 1c000001
 Signed 16 bit LAfter writing McASP4.PDIR = 1c000001
ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS
te 48000 Hz, SteMCASP SND_SOC_DAIFMT_IB_NF
reo
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw data '04Track.raw' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
MCASP Port Format setting begins
Before writing McASP4.PDIR = 1c000001
After writing McASP4.PDIR = 1c000001
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_IB_NF
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 1c000001
 Signed 16 bit LAfter writing McASP4.PDIR = 1c000001
ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS
te 48000 Hz, SteMCASP SND_SOC_DAIFMT_IB_NF
reo
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# devmem2 0x4a1a8014
/dev/mem opened.
Memory mapped at address 0x400bd000.
Read at address  0x4A1A8014 (0x400bd014): 0x1C000001

root@c6a811x-evm:/home/PCM# devmem2 0x4a1a8014
/dev/mem opened.
Memory mapped at address 0x400fb000.
Read at address  0x4A1A8014 (0x400fb014): 0x1C000001

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 1c000001
 Signed 16 bit LAfter writing McASP4.PDIR = 1c000001
ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS
te 48000 Hz, SteMCASP SND_SOC_DAIFMT_IB_NF
reo
 Aborted by signal Interrupt...

root@c6a811x-evm:/home/PCM#
root@c6a811x-evm:/home/PCM# devmem2 0x4a1a8014
/dev/mem opened.
Memory mapped at address 0x4023d000.
Read at address  0x4A1A8014 (0x4023d014): 0x1C000001
root@c6a811x-evm:/home/PCM# devmem2 0x4a1a8014
/dev/mem opened.
Memory mapped at address 0x40061000.
Read at address  0x4A1A8014 (0x40061014): 0x1C000001
root@c6a811x-evm:/home/PCM#

Manju,

Can you check if your flow enters into some of the other cases:

case SND_SOC_DAIFMT_CBM_CFS:

case SND_SOC_DAIFMT_CBM_CFM:

Please make sure the flow enters only the below case:

case SND_SOC_DAIFMT_CBS_CFS:

Check also if the flow enters in the below if statement:

static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,

   unsigned int freq, int dir)

{

struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);

if (dir == SND_SOC_CLOCK_OUT) {

mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);

mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);

mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);

 

BR
Pavel

Dear Pavel,

Flow enters always in case SND_SOC_DAIFMT_CBS_CFS this is for sure happening.

static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);

if (dir == SND_SOC_CLOCK_OUT) {
printk("Setting MCASP as Clock out...!\n");
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
printk("Setting complete MCASP as Clock out...!\n");
} else {
mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
}

return 0;
}



root@c6a811x-evm:/home/PCM# aplay -D "hw:0,0" -c 2 -f S16_LE -r 48000 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
'04Track.raw' :Before writing McASP4.PDIR = 1c000001
Signed 16 bit LAfter writing McASP4.PDIR = 1c000001
ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS
te 48000 Hz, SteMCASP SND_SOC_DAIFMT_NB_IF
reo
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,2" -c 2 -f S16_LE -r 48000 04Track.ra
w
Playing raw data '04Track.raw' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
MCASP Port Format setting begins
Before writing McASP4.PDIR = 1c000001
After writing McASP4.PDIR = 1c000001
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -f S16_LE -r 48000 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
'04Track.raw' :Before writing McASP4.PDIR = 0
Signed 16 bit LAfter writing McASP4.PDIR = 14000000
ittle Endian, RaMCASP SND_SOC_DAIFMT_CBS_CFS
te 48000 Hz, SteMCASP SND_SOC_DAIFMT_IB_NF
reo
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
aplay: pcm_write:1694: write error: Input/output error

Manju,

I do not find the "davinci_mcasp_set_sysclk" function in the default davinci-mcasp.c file. From where you get the instructions to add this function in the davinci-mcasp.c file?

BR
Pavel

Dear Pavel,

Misael, told to back port this function from present mcasp.c.In order set proper bit clock value for the Master configuration.
So,i did that. you can see my previous post.