J5 -Eco: Bit clock and frame sync generation from MCLK confirmation code

Manju,

Can you have a try with the below modification:

if (dir == SND_SOC_CLOCK_OUT) {

//mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);

//mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);

//mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);

} else {

After this modification, see if you have clock signals on McASP0/2/4 CLKX pins, and check about the values in McASP0/2/4 PDIR and AHCLKXCTL registers.

BR
Pavel

Dear Pavel,

No clock on MCASP4.

Below is the log:

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,0" -c 2 -r 48000 -f S16_LE 04Track.raw
Playing raw dataMCASP Port Format setting begins
'04Track.raw' :Before writing McASP4.PDIR = 0
Signed 16 bit LBefore writing McASP0.PDIR = 0
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 8000
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 0
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 0
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8000
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
aplay: pcm_write:1694: write error: Input/output error


root@c6a811x-evm:/home/PCM# aplay -D "hw:0,0" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw data '04Track.raw' : Signed 16 bit Little Endian, Rate 48000 Hz, Stereo
MCASP Port Format setting begins
Before writing McASP4.PDIR = 0
Before writing McASP0.PDIR = 14000000
Before writing McASP2.PDIR = 0
Before writing McASP4.AHCLKXCTL = 8000
Before writing McASP0.AHCLKXCTL = 8007
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 0
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 0
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8007
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
aplay: pcm_write:1694: write error: Input/output error


root@c6a811x-evm:/home/PCM# aplay -D "hw:0,2" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
'04Track.raw' :Before writing McASP4.PDIR = 0
Signed 16 bit LBefore writing McASP0.PDIR = 14000000
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 8007
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 0
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 14000000
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8007
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!


root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.ra
w
Playing raw dataMCASP Port Format setting begins
'04Track.raw' :Before writing McASP4.PDIR = 0
Signed 16 bit LBefore writing McASP0.PDIR = 14000000
ittle Endian, RaBefore writing McASP2.PDIR = 14000001
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 8007
Before writing McASP2.AHCLKXCTL = 8007
After writing McASP4.PDIR = 14000000
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 14000001
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8007
After writing McASP2.AHCLKXCTL = 8007
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_IB_NF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
aplay: pcm_write:1694: write error: Input/output error

manju gunnaiah said:

No clock on MCASP4.

Do you mean there is clock on McASP0/2 ACLKX pin, but no clock on McASP4 ACLKX pin?

Provide me the values in McASP0/2/4 PDIR and AHCLKXCTL registers after the aplay command, using devmem2.

BR
Pavel

Dear Pavel,

Yes there is clock on McASP0/2 ACLKX pin. But no clock on on McASP4_ACLKX pin,

Below is the log for devmem2:

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.raw----------MCASP4
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 0
 Signed 16 bit LBefore writing McASP0.PDIR = 0
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 8000
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 14000000
After writing McASP0.PDIR = 0
After writing McASP2.PDIR = 0
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8000
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_IB_NF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# devmem2 0x4a1a8014
/dev/mem opened.
Memory mapped at address 0x401e7000.
Read at address  0x4A1A8014 (0x401e7014): 0x14000001

root@c6a811x-evm:/home/PCM# devmem2 0x4a1a80b4
/dev/mem opened.
Memory mapped at address 0x402bc000.
Read at address  0x4A1A80B4 (0x402bc0b4): 0x00188000

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,0" -c 2 -r 48000 -f S16_LE 04Track.raw-----------------MCASP0
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 14000001
 Signed 16 bit LBefore writing McASP0.PDIR = 0
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 188000
reo
Before writing McASP0.AHCLKXCTL = 8000
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 14000001
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 0
After writing McASP4.AHCLKXCTL = 188000
After writing McASP0.AHCLKXCTL = 8000
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
aplay: pcm_write:1694: write error: Input/output error

root@c6a811x-evm:/home/PCM# devmem2 0x48038014
/dev/mem opened.
Memory mapped at address 0x402f7000.
Read at address  0x48038014 (0x402f7014): 0x14000000

root@c6a811x-evm:/home/PCM# devmem2 0x480380B4
/dev/mem opened.
Memory mapped at address 0x400a3000.
Read at address  0x480380B4 (0x400a30b4): 0x00008007

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,2" -c 2 -r 48000 -f S16_LE 04Track.raw-------------------MCASP2
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 14000001
 Signed 16 bit LBefore writing McASP0.PDIR = 14000000
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 188000
reo
Before writing McASP0.AHCLKXCTL = 8007
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 14000001
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 14000000
After writing McASP4.AHCLKXCTL = 188000
After writing McASP0.AHCLKXCTL = 8007
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider

root@c6a811x-evm:/home/PCM# devmem2 0x48050014
/dev/mem opened.
Memory mapped at address 0x402d1000.
Read at address  0x48050014 (0x402d1014): 0x14000001

root@c6a811x-evm:/home/PCM# devmem2 0x480500B4
/dev/mem opened.
Memory mapped at address 0x4027e000.
Read at address  0x480500B4 (0x4027e0b4): 0x00008007
root@c6a811x-evm:/home/PCM#

Below is my clock settings for MCASP0/2/4 ports:

clk_enable_init_clocks();

//Selecting AUDIO_CLK_IN0 to MCASP0/2/4 AHCLKX pins Manju.G

if (cpu_is_ti81xx()) {

clkp0 = clk_get(NULL,"mcasp1_ahx_ck");

    if(!clkp0) printk("MCASP0 AHCLKX clk_get failed\n");

    else printk("MCASP0 AHCLKX clk_get successed.\n");

clkp2 = clk_get(NULL,"mcasp3_ahx_ck");

    if(!clkp2) printk("MCASP2 AHCLKX clk_get failed\n");

    else printk("MCASP2 AHCLKX clk_get successed.\n");

clkp4 = clk_get(NULL,"mcasp5_ahx_ck");

    if(!clkp4) printk("MCASP4 AHCLKX clk_get failed\n");

    else printk("MCASP4 AHCLKX clk_get successed.\n");

    new_parent = clk_get(NULL,"xref0_ck");

    if(!new_parent) printk("AUDIO_CLK_IN0 clk_get failed\n");

    else printk("AUDIO_CLK_IN0 clk_get successed.\n");

clk_enable(new_parent);

  ret0=clk_set_parent(clkp0, new_parent);

if(ret0==-EINVAL)

printk("MCASP0 parent clock setting invalid.\n");

else if(ret0==-EBUSY)

printk("MCASP0 parent clock setting busy.\n");

else

printk("MCASP0 parent clock setting successed.\n");

ret2=clk_set_parent(clkp2, new_parent);

if(ret2==-EINVAL)

printk("MCASP2 parent clock setting invalid.\n");

else if(ret2==-EBUSY)

printk("MCASP2 parent clock setting busy.\n");

else

printk("MCASP2 parent clock setting successed.\n");

ret4=clk_set_parent(clkp4, new_parent);

if(ret4==-EINVAL)

printk("MCASP4 parent clock setting invalid.\n");

else if(ret4==-EBUSY)

printk("MCASP4 parent clock setting busy.\n");

else

printk("MCASP4 parent clock setting successed.\n");

clk_enable(clkp0);

clk_enable(clkp2);

clk_enable(clkp4);

clk_put(clkp0);

clk_put(clkp2);

clk_put(clkp4);

}

Can you have a try with the below modification:

if (dir == SND_SOC_CLOCK_OUT) {

//mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);

mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);

//mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);

//mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);

} else {

After this modification, check if you have clock signal on McASP0/2/4 ACLKX pin and provide me the values in McASP0/2/4 PDIR and AHCLKXCTL registers after the aplay command, using devmem2

BR
Pavel

Dear Pavel,

Now i'm getting the MCASP4 clock along with the MCASP0 and MCASP2.

But frame sync are  not proper as expected.Whether we need to adjust clock divider for frame sync also?

As per clkdiv driver code we can divide Bit clock too:

static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
{
    struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);

    switch (div_id) {
    case 0:        /* MCLK divider */
        mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
                   AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
        mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
                   AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
        printk("Entered MCLK divider\n");
        break;

    case 1:        /* BCLK divider */
        mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
                   ACLKXDIV(div - 1), ACLKXDIV_MASK);
        mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
                   ACLKRDIV(div - 1), ACLKRDIV_MASK);
        printk("Entered BCLK divider\n");
        break;

    case 2:        /* BCLK/LRCLK ratio */
        dev->bclk_lrclk_ratio = div;
        printk("Entered BCLK/LRCLK ratio\n");
        break;

    default:
        return -EINVAL;
    }

    return 0;
}

But there is issue on data, it is not transmitted on MCASP_AXR0 and MCASP_AXR1 pins. Below is the logs along with devmem2 values:

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,0" -c 2 -r 48000 -f S16_LE 04Track.raw-------------------------------MCASP0
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 0
 Signed 16 bit LBefore writing McASP0.PDIR = 0
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 8000
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 0
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 0
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8000
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
aplay: pcm_write:1694: write error: Input/output error
root@c6a811x-evm:/home/PCM# devmem2 0x48038014
/dev/mem opened.
Memory mapped at address 0x402aa000.
Read at address  0x48038014 (0x402aa014): 0x14000000
root@c6a811x-evm:/home/PCM# devmem2 0x480380B4
/dev/mem opened.
Memory mapped at address 0x402b5000.
Read at address  0x480380B4 (0x402b50b4): 0x00000007

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,2" -c 2 -r 48000 -f S16_LE 04Track.raw------------------------------MCASP2
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 0
 Signed 16 bit LBefore writing McASP0.PDIR = 14000000
ittle Endian, RaBefore writing McASP2.PDIR = 0
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 7
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 0
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 14000000
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 7
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
underrun!!! (at least 0.146 ms long)
underrun!!! (at least 0.604 ms long)
underrun!!! (at least 0.036 ms long)
underrun!!! (at least 0.243 ms long)
underrun!!! (at least 0.409 ms long)
underrun!!! (at least 0.570 ms long)
underrun!!! (at least 0.325 ms long)
underrun!!! (at least 0.284 ms long)
underrun!!! (at least 0.124 ms long)
underrun!!! (at least 0.112 ms long)
aplay: pcm_write:1694: write error: Input/output error
root@c6a811x-evm:/home/PCM# devmem2 0x48050014
/dev/mem opened.
Memory mapped at address 0x40200000.
Read at address  0x48050014 (0x40200014): 0x14000001
root@c6a811x-evm:/home/PCM# devmem2 0x480500B4
/dev/mem opened.
Memory mapped at address 0x4026f000.
Read at address  0x480500B4 (0x4026f0b4): 0x00000007

root@c6a811x-evm:/home/PCM# aplay -D "hw:0,1" -c 2 -r 48000 -f S16_LE 04Track.raw---------------------------------------MCASP4
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :Before writing McASP4.PDIR = 0
 Signed 16 bit LBefore writing McASP0.PDIR = 14000000
ittle Endian, RaBefore writing McASP2.PDIR = 14000001
te 48000 Hz, SteBefore writing McASP4.AHCLKXCTL = 8000
reo
Before writing McASP0.AHCLKXCTL = 7
Before writing McASP2.AHCLKXCTL = 7
After writing McASP4.PDIR = 14000000
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 14000001
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 7
After writing McASP2.AHCLKXCTL = 7
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
Entered MCLK divider
underrun!!! (at least 0.168 ms long)
underrun!!! (at least 0.040 ms long)
underrun!!! (at least 0.536 ms long)
aplay: pcm_write:1694: write error: Input/output error
root@c6a811x-evm:/home/PCM# devmem2 0x4A1A8014
/dev/mem opened.
Memory mapped at address 0x40243000.
Read at address  0x4A1A8014 (0x40243014): 0x14000001
root@c6a811x-evm:/home/PCM# devmem2 0x4A1A80B4
/dev/mem opened.
Memory mapped at address 0x40338000.
Read at address  0x4A1A80B4 (0x403380b4): 0x00180000

manju gunnaiah said:

But frame sync are  not proper as expected.Whether we need to adjust clock divider for frame sync also?

Do you mean you have no FS signal on AFSX pins (MCA[0]_AFSX/AH4, MCA[2]_AFSX/AF9 and MCA[4]_AFSX/AD3)? Or you have signals, but it is not
with the frequency that you expect?

BR
Pavel

Please note that ACLKXCTL[4:0] CLKXDIV is not set in the default linux kernel code. You might be interested in the below patch, it configures McASP as master and sets the divider also:

diff --git a/sound/soc/davinci/davinci-evm.c b/sound/soc/davinci/davinci-evm.c
index 4081a54..ca9ed9a 100644
--- a/sound/soc/davinci/davinci-evm.c
+++ b/sound/soc/davinci/davinci-evm.c
@@ -38,7 +38,7 @@
#include "davinci-mcasp.h"

#define AUDIO_FORMAT (SND_SOC_DAIFMT_DSP_B | \
- SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF)
+ SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF)
static int evm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
@@ -89,6 +89,11 @@ static int evm_hw_params(struct snd_pcm_substream *substream,
if (ret < 0)
return ret;

+ /* set the cpu system clock */
+ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, 20000000, SND_SOC_CLOCK_OUT);
+ if (ret < 0)
+ return ret;
+
return 0;
}

diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 7b17d6d..a0ad06b 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -342,6 +342,45 @@ static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
printk(KERN_ERR "GBLCTL write error\n");
}

+static int davinci_config_clock(struct davinci_audio_dev *dev,
+ int rate, int slot_size)
+{
+ void __iomem *base = dev->base;
+ u32 bclk, div;
+ printk("[%s] rate:%d slot_size:%d \n",__func__, rate, slot_size);
+
+ if (dev->sysclk_freq == 0 || dev->mclk_freq == 0) {
+ printk(KERN_NOTICE "Invalid clock value\n");
+ return 0;
+ }
+
+ div = (dev->sysclk_freq / dev->mclk_freq) - 1;
+ mcasp_mod_bits(base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(div), AHCLKXDIV(0xFFF));
+ mcasp_mod_bits(base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRDIV(div), AHCLKRDIV(0xFFF));
+
+ /*
+ * bclk = rate * #tdm_slots * (slot_size)
+ * div = (sysclk / bclk) - 1
+ *
+ * for example
+ * rate = 48000 - rate sometime known as fs or sample rate
+ * tdm_slot = 2 - standard i2s format
+ * slot_size = 32 - standard i2s format for bits per slot
+ * mclk = 12288000 - from hardware spec.
+ *
+ * bclk = 48000 * 2 * 16 = 1536000
+ * div = (12288000 / 1536000) - 1 = 7
+ */
+ bclk = rate * dev->tdm_slots * slot_size;
+ div = ((dev->mclk_freq + (bclk - 1)) / bclk) - 1;
+
+ mcasp_mod_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXDIV(div), 0x1F);
+ mcasp_mod_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRDIV(div), 0x1F);
+
+ return 0;
+}
+
+
static void mcasp_start_rx(struct davinci_audio_dev *dev)
{
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
@@ -736,6 +775,8 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
int word_length;
u8 fifo_level;

+ davinci_config_clock(dev, params_rate(params),params_format(params) * 8);
+
davinci_hw_common_param(dev, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
fifo_level = dev->txnumevt;
@@ -826,11 +867,22 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
return 0;
}

+static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
+ printk("DEBUG: [%s] freq:%d\n",__func__, freq);
+
+ dev->mclk_freq = freq;
+ dev->sysclk_freq = freq;
+ return 0;
+}
static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
.startup = davinci_mcasp_startup,
.trigger = davinci_mcasp_trigger,
.hw_params = davinci_mcasp_hw_params,
.set_fmt = davinci_mcasp_set_dai_fmt,
+ .set_sysclk = davinci_mcasp_set_sysclk,

};

diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h
index 280c277..348e405 100644
--- a/sound/soc/davinci/davinci-mcasp.h
+++ b/sound/soc/davinci/davinci-mcasp.h
@@ -68,6 +68,8 @@ struct davinci_audio_dev {
* configure the McASP driver PIN_DIR
*/
int clk_input_pin;
+ u32 mclk_freq;
+ u32 sysclk_freq;
};

#endif /* DAVINCI_MCASP_H */

BR
Pavel

I also found you have backport davinci_mcasp_set_clkdiv() function in your davinci-mcasp.c file. Can you check if your flow enters in the below case?

static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)

{

struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);

switch (div_id) {

case 1: /* BCLK divider */

mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,

      ACLKXDIV(div - 1), ACLKXDIV_MASK);

mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,

      ACLKRDIV(div - 1), ACLKRDIV_MASK);

break;

Dear Pavel,

MCASP0: I2S mode with 24-bit data and 2 channels

static u8 ti811x_iis_serializer_direction_mcasp0[] = {

    RX_MODE,    RX_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,

};

   {      .tx_dma_offset  = 0x46000000,

        .rx_dma_offset  = 0x46000000,

        .op_mode        = DAVINCI_MCASP_IIS_MODE,

        .num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp0),

        .tdm_slots      = 2,

        .serial_dir     = ti811x_iis_serializer_direction_mcasp0,

        .asp_chan_q     = EVENTQ_2,

        .version        = MCASP_VERSION_2,

        .txnumevt = 1,

         .rxnumevt = 1,

        .clk_input_pin = MCASP_AHCLKX_IN,

}

MCASP4: TDM 8-slots 32-bit MSB first

static u8 ti811x_iis_serializer_direction_mcasp4[] = {
    TX_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
};

{
    .tx_dma_offset    = 0x4A1AB000,
    .rx_dma_offset    = 0x4A1AB000,
    .op_mode    = DAVINCI_MCASP_IIS_MODE,
    .num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp4),
    .tdm_slots    = 8,
    .serial_dir    = ti811x_iis_serializer_direction_mcasp4,
    .asp_chan_q    = EVENTQ_2,
    .version    = MCASP_VERSION_2,
    .txnumevt    = 1,
    .rxnumevt    = 1,
    .clk_input_pin    = MCASP_AHCLKX_IN,
    },

MCASP0 will have now two receivers:AXR0 and AXR1  

AXR0:24-bit 2channel audio i.e, Front-Left and Front-Right

AXR1:24-bit 2channel audio i.e, Rear-Left and Rear-Right

Both AXR0 and AXR1 data needs to be received and Transmitted over MCASP4 AXR0.

How can i achieve this by using alsa readi and writei functions.Will our MCASP support two receivers to receive the data in parallel at the same time?

manju gunnaiah said:

How can i achieve this by using alsa readi and writei functions.

Do you mean snd_pcm_readi and snd_pcm_writei functions?

manju gunnaiah said:

Will our MCASP support two receivers to receive the data in parallel at the same time?

I think J5Eco McASP is able to receive data on two pins (AXR0 and AXR1) in parallel at the same time.

BR
Pavel

Dear Pavel,

Yes it is snd_pcm_readi and snd_pcm_writei functions.

This means that if i read from MCASP0, with snd_pcm_readi i will get data from both AXR0 and AXR1 at the same time ?

If i get data from AXR0 and AXR1 at the same time with snd_pcm_readi function and then if i write to MCASP4 using snd_pcm_writei function will all data from MCASP0 AXR0 and AXR1 will written in 4 slots.

For McASP4:  The AMP requires the following Format:

Fs = 48 kHz

Fsck = 256 *fs

Ws = min.: 2/Fsck and max.: 255/Fsck

 TDM8 with 32 Bit/Channel (first 24 Bit Audio Data and trailing 8 Bit stuffed with zeros) with MSB first.

To get the AMP data from the I2S Stream (McASP0) simply need to copy the channels to the McASP4

MCASP0 -->McASP4

Ch1 --->Ch1

Ch2 --> Ch2

Ch3---> Ch3

Ch4 --> Ch4

Manju,

manju gunnaiah said:

Using aplay command if i increase channel from 2 to 4 it is throwing error:

root@c6a811x-evm:/home/audiosamples# aplay -D "hw:0,1" -c 4 -r 48000 -f S32_LE 0

hw:0,1 is McASP4. On McASP4 you have only one serializer (AXR0 on TX_MODE). Do you mean you need to set multi channel playback on a single serializer (4 channels on AXR0)?

BR
Pavel

manju gunnaiah said:

If i add aplay to run in as init script for MCASP0/2/4.Then if i wan't to open the device from userspace is it possible ? Because its already opened with aplay.

I do not understand your questions. Which device will be already open?

manju gunnaiah said:

If i use snd_pcm_writei and snd_pcm_readi function i will succeed?

succeed with what?

manju gunnaiah said:

Aplay is mandatory to run the MCASP bit clock and framesync? There is no alternative setting for this?

Aplay or playback application can be used.

BR
Pavel

Dear Pavel,

When i play the sound card device "hw:0,1"(MCASP4) using aplay command: aplay -D "hw:0,1" -c 8 -f S32_LE -r 48000 track1.wav

After which if i try to access the same device i.e, "hw:0,1" its shows device busy.

So, As per your suggestion if run the aplay command for "hw:0,1" aplay -D "hw:0,1" -c 8 -f S32_LE -r 48000 as startup script in linux kernel that device will holded by the aplay.Then if i try to do snd_pcm_writei and snd_pcm_readi then it will show device busy right?.

It won't allow me to set any hardware parameters for the device "hw:0,1" from userspace.

How can i go with this

Manju,

J5Eco audio driver supports simultaneous playback and record (full-duplex mode), but does not allow opening the same stream (playback/capture) multiple times.

Make sure you have different streams for playback and capture:

snd_pcm_t *playback_handle;
snd_pcm_stream_t stream_playback = SND_PCM_STREAM_PLAYBACK;
snd_pcm_open (&playback_handle, device, stream_playback, 0);


snd_pcm_t *capture_handle;
snd_pcm_stream_t stream_capture = SND_PCM_STREAM_CAPTURE;
snd_pcm_open (&capture_handle, device, stream_capture, 0);

Check also if there will be any improvement if you use "default" for playback and "hw:0,0" for capture/record.

BR
Pavel

Dear Pave,

I'm using different streams for playback and record from my initial code:

char           *snd_device_in  = "hw:0,0";-------------->MCASP0

char           *snd_device_out = "hw:0,1";--------------->MCASP4

snd_pcm_t      *playback_handle;

snd_pcm_t      *capture_handle;

       if ((err = snd_pcm_open(&playback_handle, snd_device_out, SND_PCM_STREAM_PLAYBACK, SND_PCM_ASYNC)) < 0) {

               printf("Playback open error:%s : %s\n", snd_device_out, snd_strerror(err));

               exit(1);

       }

       if ((err = snd_pcm_open(&capture_handle,snd_device_in, SND_PCM_STREAM_CAPTURE, SND_PCM_ASYNC)) < 0) {

               printf("Record open error: %s :%s\n", snd_device_in, snd_strerror(err));

               exit(1);

       }

But still no improvement.

capture device doesn't open after playback device.

If swap the positions then capture device will open but playback device doesn't.

After using aplay for failed device opening.Then if i run application both device opens.

Manju,

I check this on my side, and it works fine, I can open both playback and capture devices:

root@dm814x-evm:~# aplay -l

**** List of PLAYBACK Hardware Devices ****

card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []

 Subdevices: 1/1

 Subdevice #0: subdevice #0

card 0: EVM [TI81XX EVM], device 1: hdmi HDMI-DAI-CODEC-1 []

 Subdevices: 1/1

 Subdevice #0: subdevice #0

root@dm814x-evm:~# arecord -l

**** List of CAPTURE Hardware Devices ****

card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []

 Subdevices: 1/1

 Subdevice #0: subdevice #0

root@dm814x-evm:~# ./minimal_playback_capture

capture snd_pcm_open err = 0

playback snd_pcm_open err = 0

snd_pcm_readi successful

I compile with below Makefile:

minimal_playback_capture:
# Make sure that you use a tab below
    $(CSTOOL_PREFIX)gcc -I/home/users/pbotev/ti-ezsdk_dm814x-evm_5_05_02_00/linux-devkit/arm-none-linux-gnueabi/usr/include/ -L/home/users/pbotev/ti-ezsdk_dm814x-evm_5_05_02_00/linux-devkit/arm-none-linux-gnueabi/usr/lib/ -lasound -o minimal_playback_capture minimal_playback_capture.c

The application is as below:

#include <stdio.h>
#include <stdlib.h>
#include <alsa/asoundlib.h>

#define BUFF_SIZE 4096

int main (int argc, char *argv[])
{
  int err;
  short buf[BUFF_SIZE];
  int rate = 44100; /* Sample rate */
  int exact_rate; /* Sample rate returned by */
  snd_pcm_t *playback_handle;
  snd_pcm_t *capture_handle;

  /* This structure contains information about the hardware and can be used to specify the configuration to be used for */
  /* the PCM stream. */
  snd_pcm_hw_params_t *hw_params;

  /* Name of the PCM device, like hw:0,0 */
  /* The first number is the number of the soundcard, the second number is the number of the device. */
  static char *cdevice = "plughw:0,0"; /* capture device */ //McASP2
  static char *pdevice = "plughw:0,1"; /* playback device */ //HDMI

  /* Open PCM. The last parameter of this function is the mode. */
  if ((err = snd_pcm_open (&capture_handle, cdevice, SND_PCM_STREAM_CAPTURE, 0)) < 0) {
    fprintf (stderr, "cannot open audio device (%s)\n", snd_strerror (err));
    exit (1);
  }
   printf("capture snd_pcm_open err = %d\n",err);
    
  /* Open PCM. The last parameter of this function is the mode. */
  if ((err = snd_pcm_open (&playback_handle, pdevice, SND_PCM_STREAM_PLAYBACK, 0)) < 0) {
    fprintf (stderr, "cannot open audio device (%s)\n", snd_strerror (err));
    exit (1);
  }
   printf("playback snd_pcm_open err = %d\n",err);

  memset(buf,0,BUFF_SIZE);

Can you provide me the below things:

1. Your Makefile. If you do not use Makefile, please provide me details about how exactly you create/build/make your executable

2. The output of "aplay -l" and "arecord -l"

3. Your C file

BR
Pavel

Dear Pavel,

Below are the details:

root@c6a811x-evm:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 1: AIC3X tlv320aic3x-hifi-1 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 2: AIC3X tlv320aic3x-hifi-2 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

root@c6a811x-evm:~# arecord -l
**** List of CAPTURE Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 1: AIC3X tlv320aic3x-hifi-1 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 2: AIC3X tlv320aic3x-hifi-2 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

8585.mcasp_test.c

4336.Makefile.txt

Manju,

Below is the beginning of your application:

int main (int argc, char *argv[])

{

int             restarting;

int err=0;

int err1=0;

int             fragments = 2;

int             pchannels = 4,cchannels=4 ,i=0;

int             buffer_size = 512,size=0;

int             bits = 32;

int catch;

int             frames, inframes, outframes, frame_size,exit_program=0;

char *rdbuf;

char           *snd_device_in  = "hw:0,0";

char           *snd_device_out = "hw:0,1";

//char           *snd_device_out = "default";

#if(0)

char           *snd_device_in  = "hw:0,0";

char           *snd_device_out = "hw:0,1";

#endif

#if(0)

char           *snd_device_in  = "hw:1,0";

char           *snd_device_out = "hw:1,0";

#endif

snd_pcm_t      *playback_handle;

snd_pcm_t      *capture_handle;

       if ((err = snd_pcm_open(&playback_handle, snd_device_out, SND_PCM_STREAM_PLAYBACK, 0)) < 0) {

               printf("Playback open error:%s : %s\n", snd_device_out, snd_strerror(err));

               exit(1);

       }

       if ((err = snd_pcm_open(&capture_handle,snd_device_in, SND_PCM_STREAM_PLAYBACK, 0)) < 0) {

               printf("Record open error: %s :%s\n", snd_device_in, snd_strerror(err));

               exit(1);

       }

Do your application give error on the below code from the extract?

if ((err = snd_pcm_open(&capture_handle,snd_device_in, SND_PCM_STREAM_PLAYBACK, 0)) < 0) {
                printf("Record open error: %s :%s\n", snd_device_in, snd_strerror(err));
                exit(1);
        }

BR
Pavel

Manju,

You are using the same stream (SND_PCM_STREAM_PLAYBACK) for both playback and capture. As we already discusses (see the below e2e post), J5Eco audio driver does not allow opening the same stream (playback/capture) multiple times.

Can you try the below modification:

if ((err = snd_pcm_open(&capture_handle,snd_device_in, SND_PCM_STREAM_CAPTURE, 0)) < 0) {

printf("Record open error: %s :%s\n", snd_device_in, snd_strerror(err));

exit(1);

}

BR
Pavel

Dear Pavel,

Sorry i have sent you file which is not correct.But I'm not using same stream you can see in my earlier post about it.I tested this with different streams.

char *snd_device_in = "hw:0,0";-------------->MCASP0

char *snd_device_out = "hw:0,1";--------------->MCASP4

snd_pcm_t *playback_handle;

snd_pcm_t *capture_handle;

if ((err = snd_pcm_open(&playback_handle, snd_device_out, SND_PCM_STREAM_PLAYBACK, SND_PCM_ASYNC)) < 0) {

printf("Playback open error:%s : %s\n", snd_device_out, snd_strerror(err));

exit(1);

}

if ((err = snd_pcm_open(&capture_handle,snd_device_in, SND_PCM_STREAM_CAPTURE, SND_PCM_ASYNC)) < 0) {

printf("Record open error: %s :%s\n", snd_device_in, snd_strerror(err));

exit(1);

}

No improvement on this

Manju,

On EVM, what is the output of "aplay -l" and "arecord -l"?

Can you modify your application like below and try on both custom board and TI EVM:

int main (int argc, char *argv[])

{

static char           *snd_device_in  = "plughw:0,0";

static char           *snd_device_out = "plughw:0,1";

...

}

Please provide me the console output when you start your application.

BR
Pavel

Dear Pavel,

I tried adding below changes:

static char           *snd_device_in  = "plughw:0,0";

static char           *snd_device_out = "plughw:0,1";

But still its the same issue.

I'm attaching my alsa.conf file.

0842.alsa.conf.txt