J5 -Eco: Bit clock and frame sync generation from MCLK confirmation code

Manju,

Can you also run the below executable on EVM and on your custom board. Let me know the console output.

evm:~# ./mcasp_test

2084.mcasp_test

BR
Pavel

manju gunnaiah said:

On EVM,
root@c6a811x-evm:/bin# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
Subdevices: 0/1
Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 1: hdmi HDMI-DAI-CODEC-1 []
Subdevices: 0/1
Subdevice #0: subdevice #0

root@c6a811x-evm:/bin# ./mcasp_test
Audio MCLK set rate failed 6144000
asoc: interface hdmi-dai hw params failed
Input buffer overrun
Input buffer overrun

It seems to be able to open both playback and capture device on the EVM. Can you enable McASP0 (mapped on hw:0,0) and McASP4 (mapped on hw:0,1) on the EVM (same as in custom board) and try the application then.

BR
Pavel

manju gunnaiah said:

On EVM enabled MCASP0 and MCASP4,

root@c6a811x-evm:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 1: AIC3X tlv320aic3x-hifi-1 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 2: hdmi HDMI-DAI-CODEC-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0

Do you map McASP0 to hw:0,0, McASP4 to hw:0,1 and HDMI to hw:0,2? What about the default McASP2? Do you remove/disable McASP2 from the kernel?

BR
Pavel

Dear Pavel,

My Mcasp0 which is clock master  which is receiving data on two receiver lines AXR0 and AXR1 from codec.

Both aplay and arecord are throwing  error,

root@c6a811x-evm:~# arecord -D "hw:0,0" -f cd -t wav -c 2 track.wav
Recording WAVE 'MCASP Port Format setting begins
track.wav' : SigMCASP SND_SOC_DAIFMT_I2S
ned 16 bit LittlBefore writing McASP4.PDIR = 0
e Endian, Rate 4Before writing McASP0.PDIR = 0
Before writing McASP2.PDIR = 0

Before writing McASP4.AHCLKXCTL = 8000
Before writing McASP0.AHCLKXCTL = 8000
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 0
After writing McASP0.PDIR = 14000000
After writing McASP2.PDIR = 0
After writing McASP4.AHCLKXCTL = 8000
After writing McASP0.AHCLKXCTL = 8000
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Sync set to Rising Edge...
 Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
MCASP4 Global Transmit control register value = 0
MCASP0 Global Transmit control register value = 0
MCASP2 Global Transmit control register value = 0
Entered BCLK divider
Later MCASP4 Global Transmit control register value = 0
Later MCASP0 Global Transmit control register value = 300
Later MCASP2 Global Transmit control register value = 0
MCASP2 AFSX control register value = 0
MCASP0 AFSX control register value = 300
MCASP4 Global Transmit control register value = 0
MCASP4 Global Transmit control register value = 0
MCASP0 Global Transmit control register value = 300
MCASP2 Global Transmit control register value = 0
Entered BCLK/LRCLK ratio
Later MCASP4 Global Transmit control register value = 0
Later MCASP0 Global Transmit control register value = 300
Later MCASP2 Global Transmit control register value = 0
MCASP2 AFSX control register value = 0
MCASP0 AFSX control register value = 300
MCASP4 Global Transmit control register value = 0
PCM format for 16-bit set
Enters the channel configuration
Enters the channel size for 16-word
mcasp start for Capture
Settings made on global control register for Receive clock
MCASP stop reception triggered
arecord: pcm_read:1785: read error: Input/output error

root@c6a811x-evm:~# aplay -D "hw:0,0" -c 8 -r 48000 -f S32_LE 04Track.raw

Playing raw dataMCASP Port Format setting begins

'04Track.raw' :MCASP SND_SOC_DAIFMT_I2S

Signed 32 bit LBefore writing McASP4.PDIR = 14000001

ittle Endian, RaBefore writing McASP0.PDIR = 14000000

te 48000 Hz, ChaBefore writing McASP2.PDIR = 0

nnels 8

Before writing McASP4.AHCLKXCTL = 0

Before writing McASP0.AHCLKXCTL = 0

Before writing McASP2.AHCLKXCTL = 8000

After writing McASP4.PDIR = 14000001

After writing McASP0.PDIR = 14000000

After writing McASP2.PDIR = 0

After writing McASP4.AHCLKXCTL = 0

After writing McASP0.AHCLKXCTL = 0

After writing McASP2.AHCLKXCTL = 8000

MCASP SND_SOC_DAIFMT_CBS_CFS

MCASP SND_SOC_DAIFMT_NB_IF

Sync set to Rising Edge...

Setting MCASP as Clock out...!

Setting complete MCASP as Clock out...!

MCASP4 Global Transmit control register value = 1300

MCASP0 Global Transmit control register value = 313

MCASP2 Global Transmit control register value = 0

Entered BCLK divider

Later MCASP4 Global Transmit control register value = 1300

Later MCASP0 Global Transmit control register value = 313

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 313

MCASP4 Global Transmit control register value = 1300

MCASP4 Global Transmit control register value = 1300

MCASP0 Global Transmit control register value = 313

MCASP2 Global Transmit control register value = 0

Entered BCLK/LRCLK ratio

Later MCASP4 Global Transmit control register value = 1300

Later MCASP0 Global Transmit control register value = 313

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 313

MCASP4 Global Transmit control register value = 1300

playback started near FSXDUR

PCM format for 32-bit set

Enters the channel configuration

Enters the channel size for 32-word

mcasp start for playback

Settings made on global control register for Transmit clock

MCASP stop transmission triggered

aplay: pcm_write:1694: write error: Input/output error

static u8 ti811x_iis_serializer_direction_mcasp0[] = {
    RX_MODE,    RX_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
};

{
     .tx_dma_offset  = 0x46000000,
         .rx_dma_offset  = 0x46000000,
         .op_mode        = DAVINCI_MCASP_IIS_MODE,
         .num_serializer = ARRAY_SIZE(ti811x_iis_serializer_direction_mcasp0),
         .tdm_slots      = 2,
         .serial_dir     = ti811x_iis_serializer_direction_mcasp0,
         .asp_chan_q     = EVENTQ_2,
         .version        = MCASP_VERSION_2,
         .txnumevt    = 16,
     .rxnumevt    = 16,
     .clk_input_pin    = MCASP_AHCLKX_IN,
    },

aplay on MCASP2 and MCASP4 are working fine and they use single serializer AXR0 in TX_MODE.I can see on oscilloscope on data lines.

Manju,

Let switch back to your custom board for a while.

manju gunnaiah said:

On custom board,
root@c6a811x-evm:/bin# ./mcasp_test
Record open error: hw:0,0 :Invalid argument

manju gunnaiah said:

root@c6a811x-evm:~# arecord -l
**** List of CAPTURE Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0

It seems to me McASP0 is mapped on hw:0,0. Do you have TVL320AIC3x codec connected to McASP0? If no, that might be the reason for the problem.

BR
Pavel

Manju,

manju gunnaiah said:

My Mcasp0 which is clock master which is receiving data on two receiver lines AXR0 and AXR1 from codec.MCASP0 is connected to codec but not TVL320AIC3x codec. Another codec DiRANA3 -SAF7751EL

Then you should change AIC3x to DiRANA for McASP0.

manju gunnaiah said:

over i2s lines.

Do you mean I2C?

BR
Pavel

Manju,

So McASP0/2/4 are configured for the same dummy codec, and McAP2/4 can transmit/output data to Amplifier successful? McASP2/4 are using only AXR0 in TX_MODE?

Can you try configure the McASP0 to transmit/output data on AXR0 (TX_MODE) only?

Please provide me the console output of the "aplay -l" and aplay command for all McASP0/2/4.

BR
Pavel

Dear Pavel,

Yes,McASP0/2/4 are configured for the same dummy codec, and McAP2/4 can transmit/output data to Amplifier successful.

Yes i configured the McASP0 to transmit/output data on AXR0 (TX_MODE) only. Below is the logs:

root@c6a811x-evm:~# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: EVM [TI81XX EVM], device 0: AIC3X tlv320aic3x-hifi-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 1: AIC3X tlv320aic3x-hifi-1 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: EVM [TI81XX EVM], device 2: AIC3X tlv320aic3x-hifi-2 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

root@c6a811x-evm:~# aplay -D "hw:0,0" -c 8 -r 48000 -f S32_LE 04Track.raw------------------------MCASP0

Playing raw data '04Track.raw' : Signed 32 bit LiMCASP Port Format setting begins

ttle Endian, RatMCASP SND_SOC_DAIFMT_I2S

e 48000 Hz, ChanBefore writing McASP4.PDIR = 0

nels 8

Before writing McASP0.PDIR = 0

Before writing McASP2.PDIR = 0

Before writing McASP4.AHCLKXCTL = 8000

Before writing McASP0.AHCLKXCTL = 8000

Before writing McASP2.AHCLKXCTL = 8000

After writing McASP4.PDIR = 0

After writing McASP0.PDIR = 14000000

After writing McASP2.PDIR = 0

After writing McASP4.AHCLKXCTL = 8000

After writing McASP0.AHCLKXCTL = 8000

After writing McASP2.AHCLKXCTL = 8000

MCASP SND_SOC_DAIFMT_CBS_CFS

MCASP SND_SOC_DAIFMT_NB_IF

Sync set to Rising Edge...

Setting MCASP as Clock out...!

Setting complete MCASP as Clock out...!

MCASP4 Global Transmit control register value = 0

MCASP0 Global Transmit control register value = 0

MCASP2 Global Transmit control register value = 0

MCASP0 Global Receive control register value = 0

Entered BCLK divider

Later MCASP4 Global Transmit control register value = 0

Later MCASP0 Global Transmit control register value = 300

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 300

MCASP4 Global Transmit control register value = 0

MCASP4 Global Transmit control register value = 0

MCASP0 Global Transmit control register value = 300

MCASP2 Global Transmit control register value = 0

MCASP0 Global Receive control register value = 300

Entered BCLK/LRCLK ratio

Later MCASP4 Global Transmit control register value = 0

Later MCASP0 Global Transmit control register value = 300

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 300

MCASP4 Global Transmit control register value = 0

No.of serializers for MCASP ports used:16

playback started near FSXDUR

PCM format for 32-bit set

Enters the channel configuration

Enters the channel size for 32-word

mcasp start for playback

Settings made on global control register for Transmit clock

aplay: pcm_write:1694: write error: Input/output error

MCASP stop transmission triggered

root@c6a811x-evm:~# aplay -D "hw:0,1" -c 8 -r 48000 -f S32_LE 04Track.raw-----------------------------------MCASP4

Playing raw dataMCASP Port Format setting begins

'04Track.raw' :MCASP SND_SOC_DAIFMT_DSP_B

Signed 32 bit LBefore writing McASP4.PDIR = 0

ittle Endian, RaBefore writing McASP0.PDIR = 14000001

te 48000 Hz, ChaBefore writing McASP2.PDIR = 0

nnels 8

Before writing McASP4.AHCLKXCTL = 8000

Before writing McASP0.AHCLKXCTL = 0

Before writing McASP2.AHCLKXCTL = 8000

After writing McASP4.PDIR = 14000000

After writing McASP0.PDIR = 14000001

After writing McASP2.PDIR = 0

After writing McASP4.AHCLKXCTL = 8000

After writing McASP0.AHCLKXCTL = 0

After writing McASP2.AHCLKXCTL = 8000

MCASP SND_SOC_DAIFMT_CBS_CFS

MCASP SND_SOC_DAIFMT_IB_NF

Sync set to Rising Edge...

Setting MCASP as Clock out...!

Setting complete MCASP as Clock out...!

MCASP4 Global Transmit control register value = 0

MCASP0 Global Transmit control register value = 1300

MCASP2 Global Transmit control register value = 0

MCASP0 Global Receive control register value = 1300

Entered BCLK divider

Later MCASP4 Global Transmit control register value = 300

Later MCASP0 Global Transmit control register value = 1300

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 1300

MCASP4 Global Transmit control register value = 300

MCASP4 Global Transmit control register value = 300

MCASP0 Global Transmit control register value = 1300

MCASP2 Global Transmit control register value = 0

MCASP0 Global Receive control register value = 1300

Entered BCLK/LRCLK ratio

Later MCASP4 Global Transmit control register value = 300

Later MCASP0 Global Transmit control register value = 1300

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 1300

MCASP4 Global Transmit control register value = 300

No.of serializers for MCASP ports used:16

playback started near FSXDUR

Transmitter Framesync duty cycle shifts to 1-word for TDM mode

PCM format for 32-bit set

Enters the channel configuration

Enters the channel size for 32-word

mcasp start for playback

Settings made on global control register for Transmit clock

MCASP stop transmission triggered

root@c6a811x-evm:~# aplay -D "hw:0,2" -c 8 -r 48000 -f S32_LE 04Track.raw--------------------------MCASP2
Playing raw dataMCASP Port Format setting begins
 '04Track.raw' :MCASP SND_SOC_DAIFMT_I2S
 Signed 32 bit LBefore writing McASP4.PDIR = 14000001
ittle Endian, RaBefore writing McASP0.PDIR = 14000001
te 48000 Hz, ChaBefore writing McASP2.PDIR = 0
nnels 8
Before writing McASP4.AHCLKXCTL = 0
Before writing McASP0.AHCLKXCTL = 0
Before writing McASP2.AHCLKXCTL = 8000
After writing McASP4.PDIR = 14000001
After writing McASP0.PDIR = 14000001
After writing McASP2.PDIR = 14000000
After writing McASP4.AHCLKXCTL = 0
After writing McASP0.AHCLKXCTL = 0
After writing McASP2.AHCLKXCTL = 8000
MCASP SND_SOC_DAIFMT_CBS_CFS
MCASP SND_SOC_DAIFMT_NB_IF
Sync set to Rising Edge...
 Setting MCASP as Clock out...!
Setting complete MCASP as Clock out...!
MCASP4 Global Transmit control register value = 1300
MCASP0 Global Transmit control register value = 1300
MCASP2 Global Transmit control register value = 0
MCASP0 Global Receive control register value = 1300
Entered BCLK divider
Later MCASP4 Global Transmit control register value = 1300
Later MCASP0 Global Transmit control register value = 1300
Later MCASP2 Global Transmit control register value = 300
MCASP2 AFSX control register value = 300
MCASP0 AFSX control register value = 1300
MCASP4 Global Transmit control register value = 1300
MCASP4 Global Transmit control register value = 1300
MCASP0 Global Transmit control register value = 1300
MCASP2 Global Transmit control register value = 300
MCASP0 Global Receive control register value = 1300
Entered BCLK/LRCLK ratio
Later MCASP4 Global Transmit control register value = 1300
Later MCASP0 Global Transmit control register value = 1300
Later MCASP2 Global Transmit control register value = 300
MCASP2 AFSX control register value = 300
MCASP0 AFSX control register value = 1300
MCASP4 Global Transmit control register value = 1300
No.of serializers for MCASP ports used:16
playback started near FSXDUR
PCM format for 32-bit set
Enters the channel configuration
Enters the channel size for 32-word
mcasp start for playback
Settings made on global control register for Transmit clock
MCASP stop transmission triggered

Manju,

manju gunnaiah said:

no data on AXR0 (TX_MODE) pin for MCASP0.

manju gunnaiah said:

data on data pins of codec

But don't you connect AXR0 data pin to codec data pin? If not, to which codec pin you connect AXR0 data pin? I am confused because you see data on codec data pin, but do not see data on McASP0 data pin, but this should be the same pin!

manju gunnaiah said:

Pinmux for mcasp:
omap_mux_init_signal("mcasp0_aclkx_ti811x", 0 );
omap_mux_init_signal("mcasp0_fsx_ti811x", 0 );
omap_mux_init_signal("mcasp0_axr0_ti811x",0 );
omap_mux_init_signal("mcasp0_axr1_ti811x",0);


omap_mux_init_signal("mcasp2_aclkx_ti811x", 0 );
omap_mux_init_signal("mcasp2_fsx_ti811x",0 );
omap_mux_init_signal("mcasp2_axr0_ti811x",0 );
omap_mux_init_signal("mcasp2_axr1_ti811x", 0 );

omap_mux_init_signal("mcasp4_aclkx_ti811x", 0 );
omap_mux_init_signal("mcasp4_fsx_ti811x", 0 | TI814X_SLEW_SLOW);
omap_mux_init_signal("mcasp4_axr0_ti811x", 0 | TI814X_SLEW_SLOW);

Can you provide me McASP0/2/4 pinmux values after aplay command, get these with devmem2.

BR
Pavel

Dear Pavel,

MCASP0 AXR0 and AXR1 both are connected to codec chip DiRANA3.Codec Dirana3 is getting clocks from MCAP0 which is Master.

MCASP0_AXR0<----------------------------->i2s0_out_dirana3

MCASP0_AXR1<----------------------------->i2s1_out_dirana3

Data from dirana3 i2s out pins i verified on oscilloscope it showing data and the same is available to MCASP0 AXR0 and AXR1 pins also.

But MCASP0 is not able to read the data on AXR0 and AXR1 pins.

Pinmux for MCASP0, MCASP2 and MCASP4.

MCASP0

root@c6a811x-evm:~# devmem2 0x48140840
/dev/mem opened.
Memory mapped at address 0x4022f000.
Read at address  0x48140840 (0x4022f840): 0x00000001

root@c6a811x-evm:~# devmem2 0x48140844
/dev/mem opened.
Memory mapped at address 0x40356000.
Read at address  0x48140844 (0x40356844): 0x00000001

root@c6a811x-evm:~# devmem2 0x48140850
/dev/mem opened.
Memory mapped at address 0x402a5000.
Read at address  0x48140850 (0x402a5850): 0x00000001

root@c6a811x-evm:~# devmem2 0x48140854
/dev/mem opened.
Memory mapped at address 0x40261000.
Read at address  0x48140854 (0x40261854): 0x00000001

MCASP2

root@c6a811x-evm:~# devmem2 0x48140898
/dev/mem opened.
Memory mapped at address 0x402fd000.
Read at address  0x48140898 (0x402fd898): 0x00000001

root@c6a811x-evm:~# devmem2 0x4814089C
/dev/mem opened.
Memory mapped at address 0x40270000.
Read at address  0x4814089C (0x4027089c): 0x00000001

root@c6a811x-evm:~# devmem2 0x481408A0
/dev/mem opened.
Memory mapped at address 0x402e6000.
Read at address  0x481408A0 (0x402e68a0): 0x00000001

MCASP4

root@c6a811x-evm:~# devmem2 0x481408C8
/dev/mem opened.
Memory mapped at address 0x4011f000.
Read at address  0x481408C8 (0x4011f8c8): 0x00000001

root@c6a811x-evm:~# devmem2 0x481408CC
/dev/mem opened.
Memory mapped at address 0x402fd000.
Read at address  0x481408CC (0x402fd8cc): 0x00080001

root@c6a811x-evm:~# devmem2 0x481408D0
/dev/mem opened.
Memory mapped at address 0x4025a000.
Read at address  0x481408D0 (0x4025a8d0): 0x00080001

Manju,

Still not clear to me. One post you state you need to receive, other post you state you need to transmit, then start over again and again in a loop.

What I though is you try now to output/trasmit from McASP0 AXR0 to outside the device (to Dirana3). But from the your last post, it seems you need to receive on McASP0 AXR0.

manju gunnaiah said:

Data from dirana3 i2s out pins i verified on oscilloscope it showing data and the same is available to MCASP0 AXR0 and AXR1 pins also.

But MCASP0 is not able to read the data on AXR0 and AXR1 pins.

Do you need to output/transmit audio data from McASP0 AXR0 to Dirana3? Or you need to input/receive audio data from Dirana3 to McASP0 AXR0?

BR
Pavel

Manju,

Let me clarify. You need to receive/input audio data from Dirana3 to McASP0 AXR0/1 pins. And you see data signals with scope on the connections/pins between Dirana3 and McASP0 AXR0/1?

MCA[0]_AXR[0]/AH3 <-------------------- Dirana3
MCA[0]_AXR[1]/AE6 <---------------------Dirana3

The data signals goes to McASP0 AXR0/1 pins and then is lost (no data inside the McASP0 module)?

And you have for this use case the below pinmux?

MCA[0]_AXR[0]/PINCNTL21/0x48140850/AH3 = 0x00000001

MCA[0]_AXR[1]/PINCNTL22/0x48140854/AE6 = 0x00000001

BR
Pavel

Manju,

manju gunnaiah said:

MCA[0]_AXR[0]/PINCNTL21/0x48140850/AH3 = 0x00000001

MCA[0]_AXR[1]/PINCNTL22/0x48140854/AE6 = 0x00000001

These are settings for output pins. To make AXR0/1 inputs, make the below changes (I also fix bit 19 for FSX and AXR0/1):

omap_mux_init_signal("mcasp0_aclkx_ti811x", 0);
omap_mux_init_signal("mcasp0_fsx_ti811x", 0 | TI814X_SLEW_SLOW );
omap_mux_init_signal("mcasp0_axr0_ti811x",0 | TI814X_SLEW_SLOW | TI814X_INPUT_EN );
omap_mux_init_signal("mcasp0_axr1_ti811x",0 | TI814X_SLEW_SLOW | TI814X_INPUT_EN);

After these changes, check again McASP0 pins with scope, check if you have data received inside McASP0 module, and check McASP0 pinmux registers with devmem2.

BR
Pavel

Dear Pavel,

After above modification also mcasp0 is not able to receive data.

arecord -D "hw:0,0" -c 8 -r 48000 -f S32_LE -d 120 t1.raw

Recording WAVE 'tlv320aic23_write cannot write 002 to register R7

t1.raw' : SignedMCASP Port Format setting begins

32 bit Little EMCASP SND_SOC_DAIFMT_I2S

ndian, Rate 4800Before writing McASP4.PDIR = 0

0 Hz, Channels 8Before writing McASP0.PDIR = 0

Before writing McASP2.PDIR = 0

Before writing McASP4.AHCLKXCTL = 8000

Before writing McASP0.AHCLKXCTL = 8000

Before writing McASP2.AHCLKXCTL = 8000

After writing McASP4.PDIR = 0

After writing McASP0.PDIR = 14000000

After writing McASP2.PDIR = 0

After writing McASP4.AHCLKXCTL = 8000

After writing McASP0.AHCLKXCTL = 8000

After writing McASP2.AHCLKXCTL = 8000

MCASP SND_SOC_DAIFMT_CBS_CFS

MCASP SND_SOC_DAIFMT_NB_IF

Sync set to Rising Edge...

Setting MCASP as Clock out...!

Setting complete MCASP as Clock out...!

MCASP4 Global Transmit control register value = 0

MCASP0 Global Transmit control register value = 0

MCASP2 Global Transmit control register value = 0

MCASP0 Global Receive control register value = 0

Entered BCLK divider

Later MCASP4 Global Transmit control register value = 0

Later MCASP0 Global Transmit control register value = 300

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 300

MCASP4 Global Transmit control register value = 0

MCASP4 Global Transmit control register value = 0

MCASP0 Global Transmit control register value = 300

MCASP2 Global Transmit control register value = 0

MCASP0 Global Receive control register value = 300

Entered BCLK/LRCLK ratio

Later MCASP4 Global Transmit control register value = 0

Later MCASP0 Global Transmit control register value = 300

Later MCASP2 Global Transmit control register value = 0

MCASP2 AFSX control register value = 0

MCASP0 AFSX control register value = 300

MCASP4 Global Transmit control register value = 0

tlv320aic23_write cannot write 07c to register R8

tlv320aic23_write cannot write 00e to register R7

No.of serializers for MCASP ports used:16

PCM format for 32-bit set

Enters the channel configuration

Enters the channel size for 32-word

tlv320aic23_write cannot write 001 to register R9

tlv320aic23_write cannot write 045 to register R6

tlv320aic23_write cannot write 041 to register R6

tlv320aic23_write cannot write 041 to register R6

tlv320aic23_write cannot write 004 to register R5

mcasp start for Capture

Settings made on global control register for Receive clock

MCASP stop reception triggered

tlv320aic23_write cannot write 000 to register R9

tlv320aic23_write cannot write 045 to register R6

tlv320aic23_write cannot write 047 to register R6

tlv320aic23_write cannot write 047 to register R6

arecord: pcm_read:1785: read error: Input/output error

Pin mux for MCASP0:

root@c6a811x-evm:~# devmem2 0x48140840
/dev/mem opened.
Memory mapped at address 0x4027c000.
Read at address  0x48140840 (0x4027c840): 0x00000001


root@c6a811x-evm:~# devmem2 0x48140844
/dev/mem opened.
Memory mapped at address 0x402d6000.
Read at address  0x48140844 (0x402d6844): 0x00080001

root@c6a811x-evm:~# devmem2 0x48140850
/dev/mem opened.
Memory mapped at address 0x4022f000.
Read at address  0x48140850 (0x4022f850): 0x000C0001

root@c6a811x-evm:~# devmem2 0x48140854
/dev/mem opened.
Memory mapped at address 0x40200000.
Read at address  0x48140854 (0x40200854): 0x000C0001

AFSXCTL

root@c6a811x-evm:~# devmem2 0x480380AC                                          

/dev/mem opened.

Memory mapped at address 0x40223000.

Read at address  0x480380AC (0x402230ac): 0x00000112

ACLKXCTL

root@c6a811x-evm:~# devmem2 0x480380B0

/dev/mem opened.

Memory mapped at address 0x402b7000.

Read at address  0x480380B0 (0x402b70b0): 0x000000A3

AHCLKXCTL

root@c6a811x-evm:~# devmem2 0x480380B4

/dev/mem opened.

Memory mapped at address 0x402cb000.

Read at address  0x480380B4 (0x402cb0b4): 0x00000000

Manju,

manju gunnaiah said:

arecord -D "hw:0,0" -c 8 -r 48000 -f S32_LE -d 120 t1.raw

Can you try with:

arecord -D "plughw:0,0" -c 8 -r 48000 -f S32_LE -d 120 t1.raw -v

manju gunnaiah said:

tlv320aic23_write cannot write 002 to register R7

Are you using tlv320aic23 codec for McASP0? This might be the issue here.

McASP2 (default settings) use /sound/soc/codecs/tlv320aic3x.c

.codec_dai_name = "tlv320aic3x-hifi",
.codec_name = "tlv320aic3x-codec.1-0018",

HDMI (default settings) use /sound/soc/codecs/ti81xx_hdmi.c

.codec_dai_name = "HDMI-DAI-CODEC",     /* DAI name */
.codec_name = "hdmi-dummy-codec",

While your McASP0 seems to use /sound/soc/codecs/tvl320aic23.c. Can you check why?

You might need Darina3 codec driver or at least use dummy codec driver. See the below pointers for more info:

1. processors.wiki.ti.com/index.php/TI811X_PSP_AUDIO_Driver_User_Guide#FAQ - Add the support in ALSA SoC Driver

2. processors.wiki.ti.com/index.php/TI811X_PSP_AUDIO_Driver_User_Guide#FAQ > Audio.zip -> Audio.ppt -> Using a different Codec

3.

Your McASP0 pinmux settings looks correct now. Please provide me the values of all the McASP0 registers (base address 0x48038000) after arecord, take them with devmem2.

BR
Pavel

Dear Pavel,

Earlier MCASP0, MCASP2 and MCASP4 use tlv320aic3x codec driver.

To resolve alsa multiple device opening issue.I gave MCASP0 to refer codec driver for tlv320aic23.

MCASP0 and MCASP4 still use tlv320aic3x codec driver.

Darina3 codec driver is not required as it has firmware already in it.It is initilaized from userspace application using I2C.

So no Codec driver is required.

Instead of dummy driver i have given reference to tlv320aic23(MCASP0) and tlv320aic3x(MCASP2,MCASP4) codec driver.

Below is the pinmux after arecord:

root@c6a811x-evm:~# devmem2 0x48140840

/dev/mem opened.

Memory mapped at address 0x40319000.

Read at address  0x48140840 (0x40319840): 0x00000001

root@c6a811x-evm:~# devmem2 0x48140844

/dev/mem opened.

Memory mapped at address 0x40221000.

Read at address  0x48140844 (0x40221844): 0x00080001

root@c6a811x-evm:~# devmem2 0x48140850

/dev/mem opened.

Memory mapped at address 0x402b8000.

Read at address  0x48140850 (0x402b8850): 0x000C0001

root@c6a811x-evm:~# devmem2 0x48140854

/dev/mem opened.

Memory mapped at address 0x40215000.

Read at address  0x48140854 (0x40215854): 0x000C0001

manju gunnaiah said:

Earlier MCASP0, MCASP2 and MCASP4 use tlv320aic3x codec driver.

To resolve alsa multiple device opening issue.I gave MCASP0 to refer codec driver for tlv320aic23.

Does this resolve the multiple device opening issue?

If you give McASP0 the hdmi codec, will be there any improvement?

If you give McASP0 the tvl320aic3x codec, will be there any improvement?

I think you should also try with dummy codec driver for McASP0 (I provide hints for dummy codec driver in my previous post).

manju gunnaiah said:

Below is the pinmux after arecord

Your McASP0 pinmux settings looks correct. Please provide me the values of all the McASP0 registers (base address 0x48038000) after arecord, take them with devmem2.

BR
Pavel

Dear Pavel,

Please find the attached MCASP0 base registers.2548.MCASP_REGISTER_DUMPS.pdf

Dear Pavel,

Please find the attached McASP0 registers (base address 0x48038000) after arecord,

8206.MCASP_REGISTER_DUMPS.pdf

Dear Misael,

As per your suggestion i modified below mux lines:

omap_mux_init_signal("mcasp0_axr0_ti811x",1 | TI814X_SLEW_SLOW | TI814X_INPUT_EN );

omap_mux_init_signal("mcasp0_axr1_ti811x",1 | TI814X_SLEW_SLOW | TI814X_INPUT_EN);

But still read is failing when i run arecord :arecord -D "hw:0,0" -c 8 -r 48000 -f S32_LE -d 120 t1.raw

arecord: pcm_read:1785: read error: Input/output error

I have attached the register dump while running arecord command for MCASP0.

1307.MCASP0_RX_REGISTER_DUMPS.xlsx

Dear Pavel,

To test the driver i configured MCASP2 as receiver with same format as MCASP0.

But MCASP2 is receiving and arecord command is successful it recorded for 120 secs in desired audio format.

MCASP0 failed with error when i use arecord command.

Dear Pavel,

I'm able to Transmit and receive from AXR0 and only Transmit over AXR1.

I got these result by below settings:

In devices.c
, mux for pins:

omap_mux_init_signal("mcasp0_aclkx_ti811x", 0);
    omap_mux_init_signal("mcasp0_fsx_ti811x",   0 | TI814X_SLEW_SLOW | TI814X_PULL_DIS );
    omap_mux_init_signal("mcasp0_axr0_ti811x",  0 | TI814X_SLEW_SLOW | TI814X_INPUT_EN | TI814X_PULL_DIS );
    omap_mux_init_signal("mcasp0_axr1_ti811x",  0 | TI814X_SLEW_SLOW | TI814X_INPUT_EN | TI814X_PULL_DIS);

In board file,

static u8 ti811x_iis_serializer_direction_mcasp0[] = {
    TX_MODE(AXR0),    RX_MODE(AXR1),    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,
};

Serializer direction  if i set to TX_MODE for AXR0 which is able to transmit and receive over the same pin.

Then, if i set AXR0 pin as  INACTIVE_MODE and Make AXR1 as TX_MODE its is able to only transmit, but receiving failed.

If i set both AXR0 and AXR1 serializer direction to RX_MODE neither transmit nor receive is happening.

Why is this changing for MCASP0.Even though MCASP2 is also configured in the same I2S mode.

manju gunnaiah said:

Earlier MCASP0, MCASP2 and MCASP4 use tlv320aic3x codec driver.

To resolve alsa multiple device opening issue.I gave MCASP0 to refer codec driver for tlv320aic23.

Does this resolve the multiple device opening issue?

If you give McASP0 the hdmi codec, will be there any improvement?

If you give McASP0 the tvl320aic3x codec, will be there any improvement?

I think you should also try with dummy codec driver for McASP0 (I provide hints for dummy codec driver in my previous post).

Can you also provide me the latest version of your davinci-evm.c file?

BR
Pavel

Dear Pavel,

I'm able to Transmit and receive from AXR0 and only Transmit over AXR1.

I got these result by below settings:

In devices.c

, mux for pins:

omap_mux_init_signal("mcasp0_aclkx_ti811x", 0);

   omap_mux_init_signal("mcasp0_fsx_ti811x",   0 | TI814X_SLEW_SLOW | TI814X_PULL_DIS );

   omap_mux_init_signal("mcasp0_axr0_ti811x",  0 | TI814X_SLEW_SLOW | TI814X_INPUT_EN | TI814X_PULL_DIS );

   omap_mux_init_signal("mcasp0_axr1_ti811x",  0 | TI814X_SLEW_SLOW | TI814X_INPUT_EN | TI814X_PULL_DIS);

In board file,

static u8 ti811x_iis_serializer_direction_mcasp0[] = {

   TX_MODE(AXR0),    RX_MODE(AXR1),    INACTIVE_MODE,    INACTIVE_MODE,

   INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,

   INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,

   INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,    INACTIVE_MODE,

};

Serializer direction  if i set to TX_MODE for AXR0 which is able to transmit and receive over the same pin.

Then, if i set AXR0 pin as  INACTIVE_MODE and Make AXR1 as TX_MODE its is able to only transmit, but receiving failed.

If i set both AXR0 and AXR1 serializer direction to RX_MODE neither transmit nor receive is happening.

Why is this changing for MCASP0.Even though MCASP2 is also configured in the same I2S mode.

Please find the attached davinci_evm.c file1307.davinci-evm.c

manju gunnaiah said:

If i set both AXR0 and AXR1 serializer direction to RX_MODE neither transmit nor receive is happening.

Why is this changing for MCASP0.Even though MCASP2 is also configured in the same I2S mode.

Compare the HW design, pinmux and registers settings between McASP0 and McASP2 and align.

BR
Pavel

Manju,

There is no external pull down resistor attached on the MCASP2 AXR1 (RX_MODE) pin on the J5Eco EVM. Can you double check this?

Also I have test the below configurations:

TX_MODE (AXR0), RX_MODE (AXR1) - this is the default configuration, it works fine.

INACTIVE_MODE (AXR0), RX_MODE (AXR1) - works fine, I have t1.raw (3.1MB) file as result

RX_MODE (AXR0), RX_MODE (AXR1) - does not work, gives "arecord: pcm_read:1785: read error: Input/output error", t1.raw is only 44 bytes

I test with the below command:

evm:~# arecord -D "hw:0,0" -c 2 -r 48000 -f S32_LE -d 8 t1.raw -v

Recording WAVE 't1.raw' : Signed 32 bit Little Endian, Rate 48000 Hz, Stereo

Hardware PCM card 0 'TI81XX EVM' device 0 subdevice 0

Its setup is:

 stream       : CAPTURE

 access       : RW_INTERLEAVED

 format       : S32_LE

 subformat    : STD

 channels     : 2

 rate         : 48000

 exact rate   : 48000 (48000/1)

 msbits       : 32

 buffer_size  : 16384

 period_size  : 1024

 period_time  : 21333

 tstamp_mode  : NONE

 period_step  : 1

 avail_min    : 1024

 period_event : 0

 start_threshold  : 1

 stop_threshold   : 16384

 silence_threshold: 0

 silence_size : 0

 boundary     : 1073741824

 appl_ptr     : 0

 hw_ptr       : 0

Can you test this mode: INACTIVE_MODE (AXR0), RX_MODE (AXR1) - this works fine on TI EVM.

BR

Pavel