McASP interrupt service by CPU Data port

Hi,

We would also recommend you to use this preliminary software to setup TI's OMAP-L138 device platforms and you can get started with the MCSDK user guide as below:

http://processors.wiki.ti.com/index.php/MCSDK_OMAPL138_User_Guide_Getting_Started#Supported_Devices_and_Platforms

You can download MCSDK which supports both SYSBIOS as well Linux on the same package as below:

http://software-dl.ti.com/sdoemb/sdoemb_public_sw/mcsdk/latest1/index_FDS.html

While installing MCSDK, select the PDK_omapl138 for installing PDK. After installing  pdk_OMAPL138, it will create list of CSL & DRV examples. You could see the list LLD McASP & McBSP driver sample applications. and kindly refer the chapter exploring in the MCSDK user guide as below:

http://processors.wiki.ti.com/index.php/MCSDK_OMAPL138_User_Guide_Chapter_Exploring#Platform_Development_Kit_.28PDK.29

You could find the sample audio McASP audio playback in the following path after installing PDK (part of MCSDK) which uses EDMA ping pong buffer implementation.

~\ti\pdk_OMAPL138_1_01_00_02\packages\ti\drv\exampleProjects\MCASP_AudioExampleProject\

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

-------------------------------------------------------------------------------------------------------

Thank you for this. The code in location ti\pdk_OMAPL138_1_01_00_02\packages\ti\drv\mcasp\src did not point me to the right direction. I am setting up CPU interrupt and not DMA. And the code is very opaque for a beginner like me.

In location, \ti\quickStartOMAPL1x_rCSL\OMAPL1x\rCSL_examples\evmOMAPL138\DSP_examples\mcasp has functions McASPInit() and McASPStart() , which have similar settings to my code ( following McASP guide)..

But the code does not point out how do I stream an echo of I2S data in an interrupt.

Interrupt regsisters during McASP setup:

       mcaspRegs->RINTCTL = 0x00000000;//RX data buffer ready

mcaspRegs->XINTCTL = 0x00000060;//enabled TX frame sync and TX buffer ready interrupts

//I have defined if condition to check interrupts in ISR. I get an interrupt that is not among the interrupts I have enabled.

void I2S_ISR(void)
{
	//===========TX interrupts==================
	if((mcaspRegs->XSTAT & 0x00000020) && (mcaspRegs->XINTCTL & 0x00000020))
		//XDATA TX data ready flag. XBUF is empty and ready to be written
		{
			mcaspRegs->XBUF7	= mcaspRegs->XBUF8;
			Log_info0("Xdata int");//UART2Write(0x31);
			mcaspRegs->XSTAT 	= 0x00000020;			//Clear XDATA Flag
		}else if( (mcaspRegs->XSTAT & 0x00000040) && (mcaspRegs->XINTCTL & 0x00000080))
	{
		mcaspRegs->XBUF7	= mcaspRegs->XBUF8;
		Log_info0("X start of frame int");//UART2Write(0x31);
		mcaspRegs->XSTAT = 0x00000040;			//Clear XSTAFRM Flag
	}
	//===========RX interrupts==================
		else if (mcaspRegs->SRCTL8 & CSL_MCASP_SRCTL8_RRDY_MASK == CSL_MCASP_SRCTL8_RRDY_MASK)
	{
		//datain= mcaspRegs->RBUF8;
		mcaspRegs->XBUF7= mcaspRegs->RBUF8;
		Log_info0("R data int");//UART2Write(0x31);
		mcaspRegs->RSTAT	=	0x00000020;			//Clear RDATA Flag

	}
	else
		{
				UART2Write(0x45);
				Log_info0("OTHER INTERRUPT");
				mcaspRegs->XSTAT = 0x000001FF;			//Clear Flag
		}

}

Hi,

Then, you have to try McASP audio loopback sample application on c6748 LCDK starterware which should be more apt for the begineers since the starterware example code would be more comfortable to walkthrough. May be, you can download the c6748 starterware package from the below link:

http://software-dl.ti.com/dsps/dsps_public_sw/c6000/starterware/01_20_04_01/index_FDS.html

You could also try the starterware user guide for mcasp application

http://processors.wiki.ti.com/index.php/StarterWare_01.20.01.01_User_Guide#Example_Application_8

Thanks & regards,

Sivaraj K

-------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question.

-------------------------------------------------------------------------------------------------------

I have to concur with this. For electronic systems engineers the code examples given are quite obfuscated and do not work in the way we require. The formalisms used to make the code 'portable' (I assume that's the rationale for it) only serve to complicate reading and understanding what the code is doing.

I am also trying to establish a low latency audio processing example/starting point and I would be developing algorithms already if there were a good In/Out program example, but instead I'm left with either pulling apart opaque CSL or starterware or whatever code or spending a month or so data sheet diving.

For example, the spectrum digital example code that goes with the C5000 EVMs is great - it clearly shows all the processes and key steps that are necessary to get key peripherals working without requiring you to dive through headers within headers through definitions and structs when all you want to know is which registers are being set and in what order.

This stuff MASSIVELY reduces development time (at least an order of magnitude) on a platform and can easily make the difference between a project succeeding and failing.

Also - with regards to ease of development - I'm surprised there isn't at least an option to have GUI based configuration of the PLL, Pin multiplexing and peripheral setup in the TI-RTOS GUI (with all sorts of helpful diagrams showing where clocks are going, etc.). Not appropriate for all, but even if you change things during runtime, it gives you a known starting point. This stuff should not be an obstacle to producing innovative products on TI platforms, it should help you through as quickly as possible...

These examples are DMA, not CPU interrupt based. I have found code similar to my technique in
rCSL_examples in Quick Start OMAP L1x. It receives the data, but does not send out even though PDIR and SRCTLn registers are set for TX serializer. I enable interrupts in IER register before BIOS_start() call. please see my code snippet here in main()

	//enable IER CPU interrupt
	ICR = 0xFFFF;		//clear all interrupts
	IER = 0x000000A2;	// enable NMIE, UART(Int #5) and I2S (int # 7) as allocated to UART_ISR and McASP_ISR in app.cfg
	UART2Power();           // not relevant to my question here
	UART2Default();         // not relevant to my question here
	McASP_init();
	McASP_start();

My ISR first checks if McASP interrupt was caused due to TX empty buffer or TX start of frame. Then it checks if it was caused by Receieve Buffer ready and deals accordingly. 

void McASP_ISR(void) {
	Log_info0("Entered McASP isr");
	xstat_in = mcaspRegs->XSTAT;// store XRSTATs in case they change during ISR
	rstat_in = mcaspRegs->RSTAT;
	//===========TX interrupts==================
	if ((xstat_in & 0x00000020)
			&& (CSL_FEXT(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA)
					== CSL_MCASP_XINTCTL_XDATA_ENABLE)) {
		//XDATA[XBUF] is empty and ready to be written
		mcaspRegs->RINTCTL = 0x00000000;
		mcaspRegs->XINTCTL = 0x00000000;
		if ((rstat_in & 0x00000020)) {//&& (rstat_in & 0x00000001 == 0x00000000) from dspmm.c
			//check if new data received
			mcaspRegs->XBUF7 = (Uint32) mcaspRegs->RBUF15;  //echo back
			Log_info0("Xbuf");
			mcaspRegs->XSTAT = 0x00000020;			//Clear XDATA Flag
			mcaspRegs->RSTAT = 0x00000020;
		}
		Log_info0("outside if condition");
	} else if ((CSL_FEXT(xstat_in, MCASP_XSTAT_XSTAFRM)
			== CSL_MCASP_XSTAT_XSTAFRM_YES)
			&& (CSL_FEXT(mcaspRegs->XINTCTL, MCASP_XINTCTL_XSTAFRM)
					== CSL_MCASP_XINTCTL_XSTAFRM_ENABLE)) //&& (mcaspRegs->XINTCTL & 0x00000080)
			{
		mcaspRegs->RINTCTL = 0x00000000;
		mcaspRegs->XINTCTL = 0x00000000;
		Log_info0("X start of frame");
		mcaspRegs->XBUF7 = (Uint32) mcaspRegs->RBUF15;
		mcaspRegs->XSTAT = 0x00000040;			//Clear XSTAFRM Flag
	}
	//===========RX interrupts==================
	else if (CSL_FEXT(mcaspRegs->SRCTL15,
			MCASP_SRCTL15_RRDY) == CSL_MCASP_SRCTL15_RRDY_DATA) {
		//datain= mcaspRegs->RBUF8;
		mcaspRegs->RINTCTL = 0x00000000;
		mcaspRegs->XINTCTL = 0x00000000;
		Log_info0("Rbuf RRDY");
		if (CSL_FEXT(mcaspRegs->RSTAT,
				MCASP_RSTAT_RTDMSLOT) == CSL_MCASP_RSTAT_RTDMSLOT_ODD) {
			mcaspRegs->XBUF7 = (Uint32) mcaspRegs->RBUF15;
			Log_info0("odd");
		} else if (CSL_FEXT(rstat_in,
				MCASP_RSTAT_RTDMSLOT) == CSL_MCASP_RSTAT_RTDMSLOT_EVEN) {
			mcaspRegs->XBUF7 = 0x5555555Au;
			Log_info0("Even");
		}
		mcaspRegs->RSTAT = 0x0000FFFF; //0x00000020;			//Clear RDATA Flag

	} else if ((rstat_in & 0x00000020) && (mcaspRegs->RINTCTL & 0x00000020)) {
		if (CSL_FEXT(mcaspRegs->SRCTL15,
				MCASP_SRCTL15_RRDY) == CSL_MCASP_SRCTL15_RRDY_DATA) {
			//RX buffer ready
			mcaspRegs->RINTCTL = 0x00000000;
			mcaspRegs->XINTCTL = 0x00000000;
			Log_info0("Rbuf RSTAT");
			mcaspRegs->XBUF7 = (Uint32) mcaspRegs->RBUF15;
			mcaspRegs->RSTAT = 0x00000020;			//Clear RDATA Flag
		}
	}
	else {
		mcaspRegs->RINTCTL = 0x00000000;
		mcaspRegs->XINTCTL = 0x00000000;
		UART2Write(0x45); //send a character on UART if none of the above interrupts
		Log_info0("Other interrupt");
		mcaspRegs->XSTAT = 0x0000FFFF;			//Clear all Flags
		mcaspRegs->RSTAT = 0x0000FFFF;
	}
	mcaspRegs->XINTCTL = CSL_MCASP_XINTCTL_XDATA_MASK;		//restore interrupts
	mcaspRegs->RINTCTL = 0;
	Log_info0("Exited McASP init");
}

Is my method to write to XBUF right? The receive AXRn line is getting digital data stream, but transmit AXRn line is dead although System analyser displays all Log_info according to logical progression of code.