AM335x device tree pincontrol problem

Arndt Kritzner

Hi,

for a GPS receiver I wanted to use the 1PPS line (Pulse Per Second) with pps-gpio driver. At the CPU this is GPIO2_4.

In the dts-file (very similar to evk335x) I added the following configuration snippets:

    am33xx_pinmux: pinmux@44e10800 {
       pinctrl-names = "default";
        ...
       pps_pins: pinmux_pps_pins {
           pinctrl-single,pins = <
               0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)           /* gpmc_wen.gpio2_4 */
           >;
       };
    };

   ocp {
        ...
       pps {
           pinctrl-names = "default";
           pinctrl-0 = <&pps_pins>;
           compatible = "pps-gpio";
           gpios = <&gpio2 4 0>;
           status = "okay";
       };
   };

This compiles to a dtb without comments, but when starting the kernel I see:

[ 3.336041] pinctrl-single 44e10800.pinmux: bad data for mux pinmux_pps_pins
[ 3.343536] pinctrl-single 44e10800.pinmux: no pins entries for pinmux_pps_pins

... and PPS doen't work. I have double-checked the pins adress with the pinmux tool and I also cannot see a conflict with another muxing rule for this pin. Any ideas?

Thanks and regards

Arndt

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi Arndt,

I will ask the SW team to check this.

0 Yordan Kovachev over 9 years ago

TI__Guru**** 161600 points

Hi Arndt,

Do you include the am33xx.dtsi file in your DTS?
If yes, then you shouldn't redefine: am33xx_pinmux: pinmux@44e10800. You should use &am33xx_pinmux instead.

Best Regards,
Yordan

0 Arndt Kritzner over 9 years ago in reply to Yordan Kovachev

Intellectual 720 points

Hi Yordan,

yes I'm including am33xx.dtsi but not am33xx-bone-common.dtsi (attached below). In this case &am33xx_pinmux doesn't work (compilation to dtb fails with syntax error). It only seems to be available if am33xx-bone-common.dtsi is also included (which redefines it as I do).

Kind regards
Arndt

===================================================================
/dts-v1/;

#include "am33xx.dtsi"

/ {
model = "Logic Way GmbH DIMM-CPU12";
compatible = "lw,dimm-cpu12", "ti,am33xx";

cpus {
cpu@0 {
cpu0-supply = <&vdd_core>;
};
};

memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};

am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";

i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};

spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_clk.spi0_clk */
0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs1.spi0_cs1 */
>;
};

spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
0x108 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_col.spi1_sclk */
0x10c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_crs.spi1_d0 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxerr.spi1_d1 */
0x144 (PIN_INPUT_PULLUP | MUX_MODE2) /* rmii1_refclk.spi1_cs0 */
0x164 (PIN_INPUT_PULLUP | MUX_MODE2) /* ecap0_in_pwm0_out.spi1_cs1 */
>;
};

dcan0_pins: pinmux_dcan0_pins {
pinctrl-single,pins = <
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd3.d_can0_tx */
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_txd2.d_can0_rx */
>;
};

dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
0x168 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
>;
};

uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};

uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
0x178 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
>;
};

uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x12c (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txclk.uart2_rxd */
0x130 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxclk.uart2_txd */
>;
};

uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x134 (PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_txd3.uart3_rxd */
0x138 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd2.uart3_txd */
>;
};

mmc1_pins_default: pinmux_mmc1_pins {
pinctrl-single,pins = <
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txen.gpio3_3 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd0.gpio2_21 */
>;
};

mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
pinctrl-single,pins = <
0x0f0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x0f4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x0f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x0fC (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
>;
};

cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a0.mii2_txen */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_wait0.mii2_crs */
0x78 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ben1.mii2_col */
>;
};

cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};

davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};

pps_pins: pinmux_pps_pins {
pinctrl-single,pins = <
0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wen.gpio2_4 */
>;
};

};

ocp {
uart0: serial@44e09000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;

status = "okay";
};

uart1: serial@48022000 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;

status = "okay";
};

uart2: serial@48024000 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;

status = "okay";
};

uart3: serial@481a6000 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;

status = "okay";
};

musb: usb@47400000 {
status = "okay";

control@44e10000 {
status = "okay";
};

usb-phy@47401300 {
status = "okay";
};

usb-phy@47401b00 {
status = "okay";
};

usb@47401000 {
status = "okay";
dr_mode = "host";
};

usb@47401800 {
status = "okay";
dr_mode = "host";
};

dma-controller@07402000 {
status = "okay";
};
};

spi0: spi@48030000 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
ti,spi-num-cs = <2>;
ti,pindir-d0-out-d1-in = <1>;
spidev@0 {
spi-max-frequency = <24000000>;
reg = <0>;
compatible = "linux,spidev";
};
spidev@1 {
spi-max-frequency = <24000000>;
reg = <1>;
compatible = "linux,spidev";
};
};

spi1: spi@481a0000 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
ti,spi-num-cs = <2>;
ti,pindir-d0-out-d1-in = <1>;

spidev@0 {
spi-max-frequency = <24000000>;
reg = <0>;
compatible = "linux,spidev";
};
spidev@1 {
spi-max-frequency = <24000000>;
reg = <1>;
compatible = "linux,spidev";
};
};

i2c0: i2c@44e0b000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;

status = "okay";
clock-frequency = <400000>;

};

elm: elm@48080000 {
status = "okay";
};

pps {
pinctrl-names = "default";
pinctrl-0 = <&pps_pins>;
compatible = "pps-gpio";
gpios = <&gpio2 4 0>;
status = "okay";
};
};

vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};

vdd_core: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vdd_core";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};

};

&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};

&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};

&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;

};

&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};

&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
bus-width = <4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mmc1_pins_default>;
pinctrl-1 = <&mmc1_pins_sleep>;
cd-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
};

&mmc2 {
/* these are on the crossbar and are outlined in the
xbar-event-map element */
/*
dmas = <&edma 12
&edma 13>;
dma-names = "tx", "rx";
*/

vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
ti,non-removable;
ti,needs-special-hs-handling;
};

&dcan0 {
pinctrl-names = "default";
pinctrl-0 = <&dcan0_pins>;
status = "okay";
};

&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};

0 Yordan Kovachev over 9 years ago in reply to Arndt Kritzner

TI__Guru**** 161600 points

Which sources do you use?
I checked SDK8.0, SDK1.0 & SDK1.00.00.03 and am335x-bone-common.dtsi uses:
&am33xx_pinmux {

The only source, where I am able to find this redefinition is SDK7.0, so I guess you are referring to this release, right?
I can't see a mistake in defining the pinmux of pps_gpio.

Can you try moving the pps { node outside of the ocp { node? or if you keep it inside the ocp give it some physical address like the other nodes inside ocp:
pps: pps_gpio@0x<physical_address of gpio or other IP>

Best Regards,
Yordan

0 Arndt Kritzner over 9 years ago in reply to Yordan Kovachev

Intellectual 720 points

Hi Yordan, yes I'm using SDK7.0 sources. There is no longer a problem with the device tree configuration. The applied dtb was not the correct result of the analyzed dts. Sorry about asking non-relevant question.

Kind regards
Arndt

0 Arndt Kritzner over 9 years ago

Intellectual 720 points

Sorry for asking misleading question. Problem seemed so but was completely different. Thanks for supportiveness.

Arndt

Processors

Processors forum

AM335x device tree pincontrol problem