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AM437* Simplified Power Sequencing

burak balkuv
Intellectual 620 points
Other Parts Discussed in Thread: AM4376

Can you please clarify the Simplified Power Sequencing.

a) AM4376 datasheet specifies 

"Power source supplying VDDS3P3V_IOLDO should have a supply slew of >100us.
CAP_VDDS1P8V_IOLDO is the 1.8-V output of VDDA3P3V_IOLDO. VDDS, VDDS_CLKOUT terminals are powered
by shorting them to CAP_VDDS1P8V_IOLDO on the board."

However i don't see anywhere on SLVUAb1 app note where "VDDS_CLKOUT" pin E23 peing powered from CAP_VDDS1P8V_IOLDO.

Please confirm Pin 23 usage

b) Is The TIDRC79, AM437x Industrial EVM, using Simplified Powering Sequence ?

c) Is there a reference design that is using the Simplified Powering Sequence? If so please provide link

bb

  • 0
    TI__Guru**** 393215 points
    a) The Datasheet is the leading document. Information in it is correct.
    b) Yes.
    c) processors.wiki.ti.com/.../AM437X_EVM_Boards
  • 0 in reply to Biser Gatchev-XID
    Intellectual 620 points
    a) Please specify what to do with pin E23, Should it be connected to VDDS
    c) This design has many issues besides pin E23, pin AD3 is the connection on the schematic correct ?(processors.wiki.ti.com/.../AM437X_INDUSTRIAL_EVM_3K0008_schematic_REV1_3A.pdf)
    The www.ti.com/.../slvuab1.pdf specifies AD3 to be connected to vdd_core
  • 0 in reply to burak balkuv
    TI__Guru**** 393215 points
    First of all please specify your requirements: Will you use RTC or not?
  • 0 in reply to Biser Gatchev-XID
    Intellectual 620 points

    I have multiple applications. Neither of my applications use RTC-only mode. 

    One application  will use RTC timer funtionality without the low power  RTC-Only mode

    I will repeat the questions

    Datasheet and the TI refrence designs are in contradition.

    Clear usage of RTC modes with Simplified power sequencing is lacking

    I have 3 open questions and not getting solid answers

    a) AM4376 datasheet specifies 

    "Power source supplying VDDS3P3V_IOLDO should have a supply slew of >100us.
    CAP_VDDS1P8V_IOLDO is the 1.8-V output of VDDA3P3V_IOLDO. VDDS, VDDS_CLKOUT terminals are powered
    by shorting them to CAP_VDDS1P8V_IOLDO on the board."

    However i don't see anywhere on SLVUAb1 app note where "VDDS_CLKOUT" pin E23 peing powered from CAP_VDDS1P8V_IOLDO.

    Please confirm Pin E23 usage

    Please specify what to do with pin E23, Should it be connected to VDDS


    c)

    I was provided processors.wiki.ti.com/.../AM437X_EVM_Boards to use as a guideline for simplified Power Sequencing

    This design has many issues besides pin E23, pin AD3 is the connection on the schematic correct ?

    The www.ti.com/.../slvuab1.pdf specifies AD3 to be connected to vdd_core

    What is the correct connection of the AD3 pin?

  • 0 in reply to burak balkuv
    TI__Guru**** 393215 points

    burak balkuv said:
    Please specify what to do with pin E23, Should it be connected to VDDS

    Proceed per Datasheet guidelines: "Power source supplying VDDS3P3V_IOLDO should have a supply slew of >100us.CAP_VDDS1P8V_IOLDO is the 1.8-V output of VDDA3P3V_IOLDO. VDDS, VDDS_CLKOUT terminals are powered by shorting them to CAP_VDDS1P8V_IOLDO on the board."

    burak balkuv said:
    What is the correct connection of the AD3 pin?

    Follow the http://processors.wiki.ti.com/index.php/AM437x_Schematic_Checklist#RTC table for your use case.

    Let me try and explain the function of the internal RTC LDO:

    The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled by connecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should be sourced from an external 1.1-V power supply. If CAP_VDD_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. VDDS_RTC can be ramped independent of other supplies if RTC_PMIC_EN functionality is not required. If VDDS_RTC is ramped after VDD_CORE when internal RTC LDO is enabled, there might be a small amount of leakage current on VDD_CORE.