DDR3 interface with DM8168

Neelam singh

Hi,

In our design we are using two 4Gb (x16) ddr3 device, one each on EMIF0 and EMIF1 of DM8168? From h/w point of view this seems possible (as per section 8.3 of SPRS614D datasheet-8168). from s/w point of view is it feasible? is it feasible to access 32 bit on each EMIF with full speed ?

We are using 4Gb DDR3L -AS4C256M16D3L.

Regards

Neelam

over 9 years ago

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Neelam,

Yes you can address 1GByte RAM on each EMIF (2GByte total). See the below wiki for more info:

processors.wiki.ti.com/.../EZSDK_Memory_Map

BR
Pavel

0 Neelam singh over 9 years ago in reply to Pavel Botev

Expert 1035 points

Pavel,

According to TRM table 9.14

Table 9-14 Supported DDR3 Device Combinations(1)
NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS) MIRRORED? DDR3 EMIF WIDTH (BITS)
1 16 N 16
2 8 Y(2) 16
2 16 N 32
2 16 Y(2) 32
4 8 N 32
4 8 Y(3) 32
(1) This table is per EMIF.

If i am using 4Gb (x16) ddr3 device, one each on EMIF0 and EMIF1 of DM8168 then on single EMIF i can access only 16 bit I can not access 32 bit on Each at full speed . Mean hardware wise no issue but in this design speed will slow down, I can not access 32bit at a time ?

Please clarify ?

0 Pavel Botev over 9 years ago in reply to Neelam singh

TI__Guru**** 170625 points

Neelam,

If you use one 4Gb x16 DDR3 chip on EMIF0 and one 4Gb x16 DDR3 chip on EMIF1 (thus you will have 1GByte total), there will be speed slow down. See the below e2e thread for more info:

e2e.ti.com/.../157652

BR
Pavel

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DDR3 interface with DM8168