Hello,
I am looking at spruh73I.pdf "AM335x Sitara™ Processors Technical Reference Manual", chapter 14.3.2.13 "Packet Drop Interface":
14.3.2.13 Packet Drop Interface
The packet drop interface supports an external packet drop engine. The port 1 (and port 2) CPGMAC_SL
receive FIFO VBUSP interface signals are CPSW_3G outputs. The receive packet interface has an
associated packet drop input P1_RFIFO_DROP (P2_RFIFO_DROP). An external packet drop engine may
“snoop” the received packet header and data to determine whether or not the packet should be dropped.
If the packet is to be dropped the external logic must assert the drop signal by no later than the second
clock after the end of packet (or abort) indication from the CPGMAC_SL. The drop signal should remain
asserted until the second clock after the end of packet (or abort) indication. If the packet is not to be
dropped then the drop signal should remain deasserted. The CPGMAC_SL section contains more
information on the receive FIFO VBUSP interface signals and end of packet indication.
And can't find any information anywhere regarding these P1_RFIFO_DROP/P2_RFIFO_DROP inputs. Can anybody shade some light on this?
1) Are those physical pins? (balls) If yes, then where I can find reference?
2) Assuming that P1_RFIFO_DROP asserted, then will packet still be delivered to P0 configured as promisc in switch mode?
3) What author meant by "external packet drop engine"?
Anybody?
