CPTS PPS (Pulse-Per-Secon) using gigabit ethernet on evmk2h

Thank you for your quick reply. And I want to know how pps is supported in gigabit ehternet switch?

(1) Where are config registers?

Registers TS_Comp_Val and TS_Comp_Length can be located in the following Table 3-132 from SPRUHJ5 for 10 Gigabit Ethernet.

But they cannot be found in the following table 3-142 from SPRUGV9D  for Gigabit Ethernet. 

(2)where is pps signal pin for gigabit ehternet switch?

are you there?

Hi, Xin,

PPS is not using hardware, but software implementation. That means the TS_COMP is set with a value and when the CPTS timestamp delta matches the value, a signal is generated. For more details, please see arch/arm/boot/dts/k2hk-net.dtsi, drivers/net/ethernet/ti/cpts.c, and drivers/net/ethernet/ti/keystone_ethss2.c files on how it is implemented.

Rex

Hi Rex,

But the Guide about pps as followings makes it cleart that CPTS driver uses hardwares such as TS_COMP output, ts_comp_val[] and ts_comp_length[] register.

Or CPTS driver is not in accord with the Guide?

----------------------
The CPTS driver uses the timestamp compare (TS_COMP) output to support PPS.
The TS_COMP output is asserted for ts_comp_length[15:0] RCLK periods when the time_stamp value compares with the ts_comp_val[31:0] and the length value is non-zero. The TS_COMP rising edge occurs three RCLK periods after the values compare. A timestamp compare event is pushed into the event FIFO when TS_COMP is asserted. The polarity of the TS_COMP output is determined by the ts_polarity bit. The output is asserted low when the polarity bit is low.
----------------------

Yes, only if hardware supports the feature. If hardware does not support it, it is software implementation.

Rex

Hi, Rex,  thanks for your patience and quick reply.

(1) That is to say, for 1 gigabit ethernet, CPTS driver doesn't assert pps out at the hardware level because of lack of hardware support, only gives pps signal at the software level.

(2) What about 10 gigabit ethernet? Can I use it to generate pps out at the hardware level?

Hi, Xin,

When there is a time or reference clock adjustment, the application needs to inform the CPTS driver, and it is application's responsibility to modify the refclk frequency. If there isn't any adjustment, then the application doesn't need to make any modification. I am not sure where in the application code it should be modified.

Rex

Hi, Rex,

I think application ptp4l from linuxptp, which is used to implement PTP(Precision Time Protocol), should take care of time and reference clock adjustment.

But you mean ptp4l should be modified to make clock adjustment, although you don't know where to do it.

so, can I come to a conclusion that ptp4l officially provided cannot be directly used to test cpts/ptp although your MCSDK UG says it can?

Xin

Hi, Xin,

ptp4l is not a TI component and we are not qualified to make suggestions and comments over non-TI components. The User's Guide is the summarized info on what had been run on the EVM.

Rex

Hi, Rex,

okay, no suggestions and comments, could you give me clear and straightforward answers to:

(1) Have you ever modified ptp4l when using it to make cpts/ptp tests?

(2) Does it work for synchronizing clock between master and slaves?

Hi, Xin,

No, we didn't modify ptp4, and yes, it works.

Rex

"it works" means that ptp4l is capable of adjusting reference clock when necessary? If so, what components or drivers in TI-provided linux does it use to implement that?

Hi, Xin,

You keep asking questions in ptp4l application which TI does not own. I suggest that questions for ptp4l, such as if it is capable of frequency adjustment, be posted to the open source forum.

The frequency adjustment is through standard linux API which needs to be called from applicaton. The Linux API will call into TI driver. If the question is how this was tested in MCSDK linux, then the answer is that we tested the feature to the point where timestamp was recalculated using the new frequency but stopped due to some hardware constraints. The CPTS uses the internal clock on the KS2 EVM as the reference clock and this internal clock can not be changed. So, the test was done all the way from getting the API call to the point where timestamp was calculated using the new frequency mentioned earlier. It could not go futher to make the physical frequency change.

As far as how, when, and where the application makes the API call is not kernel's concern. The Linux standard API clock_adjtime() will make a syscall into kernel from where driver will pick up the operation and do accordingly.

Rex

By the way, the ptp4l works means that it has been used to test CPTS against KS2 EVM. For more details, please see "Testing CPTS/PTP" section in the "Exploring" chapter of the Keystone-II User's Guide. In the section, there are command examples for both slave and master.

Rex

Hi, Rex,

You got my point. I only want to know whether and how TI driver implements the physical frequency adjustment.

According to you, CPTS on EVMK2H doesn't support external adjustable clock and no relevant TI driver is supplied. Is that correct?

But the frequency adjustment is hardware-supported according to EVMK2H schematic, where there is a adjustable clock VCTCXO connected to the pin TSREFCLKP/N as followings:

And according to 66ak2h14 datasheet, RFTCLK Select Register (CPTS_RFTCLK_SEL) can be set to be TSREFCLK.

Does it mean: it is supported in hardware, but not supported in the CPTS driver due to using the internal clock as the reference clock?

Hi, Xin,

No, that's not what I said in previous email. You are right about the external clock. The EVM does not have external clock source and uses internal clock which CPTS uses as its reference clock, but the driver exists and implemented in the kernel. It was tested up to the point where it needs to physically changing the frequency.

Rex

Hi, Xin,

I have been talking to TI's hardware team about the PPS, and you are right the registers exist and the document didn't reflect them. Here is what hardware engineer says about the PPS: "Basically registers that existed on KS1 were not updated to reflect new parameters or bit field changes in existing parameters on KS2. K2E/K2L CPTS as described in their UG is closer to what K2HK has. But, it does have new fields that are not present in K2K, mainly the 64-bit clock.

The document you referred to earlier is for KS1 platform and as indicated that it does not reflect the new fields in KS2. Please refer to the K2E-GbE document, spruhz3,  for CPTS. http://www.ti.com/lit/ug/spruhz3a/spruhz3a.pdf .

Rex

Hi, Rex

Sorry, I'm a little confused about what you said "The EVM does not have external clock source".  In my opinion, the adjustable clock VCTCXO highlighted in the following picture feeds clock to CDCM6280 which generates frequency-multiplied clock to the pin TSREFCLKP/N as external clock source for CPTS.  Is that correct? Or the pin TSREFCLKP/N is not for CPTS? Or others?

Xin.

Hi, Xin,

Sorry, I am not a hardware person and this may be out of my area, but I'll try to see if I do an OK job.

The highlighted component is not what it means external/internal clock. It takes the feed from SPC_SPI1 and you should look beyond SPI. The feed to the SPI before it finally goes to VCTCXO can be from different sources, either an internal clock or some external clock sources. I am not sure if you have the schematics beyond the SOC_SPI1 which shows what gets feeded in to SPI. That will probably explains more clearly. If you don't have that part of the schematics, I will need to involve TI's hardware people.

Rex

Hi, Rex,

SOC SPI1 is from keystone2 chip and it is used to adjust frequency of the adjustable clock VCTCXO. I suggest you to resort to your hardware engineer.

And my questions are:

(1) Is there a corresponding TI driver for SOC SPI1?

(2) If yes, do you have its user guide about how to enable and use it? because MCSDK UG says "It's the application's responsibility to modify the (physical) rftclk frequency"

(3)Does the APP ptp4l call into it?

Xin