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flash nor paging management

sergio d'orazio
Intellectual 790 points
Other Parts Discussed in Thread: OMAPL138

Hi,
we are planning a new hardware board with OMAPL138.
We need to manage memory paging NOR because our memory is 128 MByte and is connected via bus Emif that handles up to 64 MByte with 2 chip select .
The other 2 chip select are busy to handle other memories .
We can use a GPIO to increase the address space . We have 2 softwares that work in flash: U-Boot and File System.
Are they the memory paging ?
How can they manage this GPIO ?
Have you an example ?

Sergio D'Orazio

  • 0
    TI__Mastermind 43955 points

    Hi Sergio,

    As per the OMAPL138 Datasheet,  to access the 128MB asynchronous devices ( such as NAND / NOR ) we need all the CS2, CS3, CS4 and CS5.

    Having said by you that the 2 chip select were busy to handle other memories, you have to check, in which mode it is configured...either in NORMAL Mode or Select Strobe mode.

    If it is a normal mode, the EMA_CS[5:2] pins behaves as typical chip select signals, remaining active
    for the duration of the asynchronous access. In this case, simultaneously, you cannot access the other memories ( with 2 chip select ) and the NOR of 128MB though you assert the address pins through GPIO. Can access only either of the memories ( NOR or other memories) at that point of time.

    If it is in select strobe mode, the EMA_CS[5:2] pins will act as a strobe and be active only during the strobe period of an access. In this case, it might be possible to access simultaneously the other memories ( with 2 chip select ) and the NOR. But switching the configuration between CS and GPIO might be little complicated depending upon which memory you are going to access at that point of time.

    The below TI WIKI will be useful to you for some reference to the  interface diagram for 128MB NOR.

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  • 0 in reply to Shankari G
    Intellectual 790 points

    Hi Shankari G,

    my hardware team propose me to connect the four CS to NOR 128MB flash. CS5 can be disconnect from NOR and connected to an FPGA through a GPIO. In this case I can see only 96MB. Do you see some software problem for this hardware configuration ?


    Sergio D'Orazio.

  • 0 in reply to sergio d'orazio
    TI__Mastermind 43955 points

    Hi sergio,

    In the last post, forget to attach the TI WIKI which shows the interface diagram for 32 MB, 64 MB NOR and 128 MB NOR.Here you go

    sergio said:
    my hardware team propose me to connect the four CS to NOR 128MB flash. CS5 can be disconnect from NOR and connected to an FPGA through a GPIO. In this case I can see only 96MB. Do you see some software problem for this hardware configuration ?

    If you disconnect the CS5 pin from NOR, you cannot access the NOR beyond 96MB !!.

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