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TIDEP0012 "DDR3 Reference Design without VTT termination using AM437x"

burak balkuv
Intellectual 620 points
Other Parts Discussed in Thread: TIDEP0012

Where are the gerbers or layout files for this eval board  located?

All I can find are the schematics in (www.ti.com/.../TIDEP0012

Neither the  the Pdf  (www.ti.com/.../tidr795) nor the DSN files(www.ti.com/.../tidr796 ) posted have the layout information.

the design guide provided does not have any layout info either

I'm looking for a layout example that does not use VTT termination

thanks

bb

  • 0
    TI__Guru*** 125430 points
    That board appears to be the Starter Kit. There's another folder under the name "Starter Kit" here:

    www.ti.com/.../tmdxsk437x

    Under Design Files there is "AM437x EVM PCB". If you open it up the contained file mentions "SK" (Starter Kit). Here's the direct link:

    www.ti.com/.../sprr208
  • 0 in reply to Brad Griffis
    Guru 20205 points

    Hi Brad,

    The balanced line topology with two 16-bit DDR3 memory devices that do not have VTT termination on the address and control signals seems to be used in AM437x Starter Kit, but this topology is not supported in AM437x datasheet (SPRS851B).

    Can the routing guidelines for this topology be provided? If not so, how is the TIDEP0012 applied to a custom board?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru*** 125430 points
    I have filed an enhancement to have this added to the DM. Unfortunately, that's not going to happen immediately so you will need a contingency plan if you want to move forward with that topology.

    I believe only the device placement (similar to Table 5-54 Placement Specifications) needs to be updated for this topology. So in order to move forward I recommend referencing the Starter Kit as well as the additional specs like keepout, bypass caps, length/skew, spacing, etc. from the DM. Those items aren't impacted.

    Once the updated DM is published you can review your system to see if you want/need to make any adjustments.
  • 0 in reply to Brad Griffis
    Guru 20205 points

    Hi Brad,

    Thank you for your reply.

    Why is the balanced line topology used in the Starter Kit regardless of the fly-by topology being recommended in DDR3 implementations?

    Our customer intends to use the balanced line topology to save board space. Is their understanding right?

    If move forward with the balanced line topology, for CK and ADDR_CTRL Routing, can the rule for one 16-Bit DDR3 Device (Figure 5-68, Figure 5-69, Figure 5-70 and Figure 5-71) in the DM be applied to two 16-Bit DDR3 Devices?

    Best regards,

    Daisuke

  • 0 in reply to Brad Griffis
    Guru 20205 points

    Hi Brad,

    Our customer moves forward based on the Starter Kit.

    I wish the updated DM is published as soon as possible.

    Best regards,

    Daisuke