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C66xx PCIe Timers

Kzk
Genius 5785 points

Hello,

I'm considering about PL_ACKTIMER and SYM_NUM. Could you tell mechanism of the Ack/Nak timer and the replay timer?

ACK_LATENCY_TIMER is described as below.
Timer Modifier for Ack/Nak Latency Timer. Increases the timer value for the Ack/Nak latency timer in increments of 64 clock cycles.

Is the clock the SYSCLK4 for fast peripherals? Is "64 clock cycles" the default value? Does the Ack/Nak timer increments of 2 clock cycles if I set ACK_LATENCY_TIMER to 2?

What will happen when the Ack/Nak latency timer expires? Is RPLY_TMR_ST set to 1 when the replay timer expires? Then, is the TLP replayed(resent)?

Regards,
Kazu

  • 0
    TI__Guru* 95265 points

    Kazu,

    When replay timer expires, the Replay Timer Timeout Status (RPLY_TMR_ST) will be set in Correctable Error Status Register (PCIE_CERR, 0x2180_1110). Then, the TLP is replayed(resent).

    For ACK/NACK latency timer, "Increases the timer value for the Ack/Nak latency timer in increments of 64 clock cycles."====> why did you get this info? I don't know exactly, it looks to me it is a counter (not a control how many cycles it increases).

    Regards, Eric

  • 0 in reply to lding
    Genius 5785 points

    Hello Eric,

    Thank you for your reply. I'd like to know appropriate values for timer. What's the relation between REPLAY_TIMER (SYM_NUM) and RPLY_LIMT (PL_ACKTIMER)? Can I think that the value as "64 clock cycles * REPLAY_TIMER * RPLY_LIMT" is expiration time for replay timer? What is the Ack/Nak latency timer?

    Regards,
    Kazu

  • 0 in reply to Kzk
    Genius 5785 points

    Hello,

    Could you tell me the information about PCIe timer?

    Regards,
    Kazu