Processor SDK RTOS for AM335x: Unusual MMU configuration code in the .cfg files of the example projects

I'm trying to go through and understand the SYS/BIOS examples (e.g. UART_BasicExample_evmAM335x_armExampleProject) in the Processor SDK RTOS for AM335x.

All the examples, have the following code at the end of their *.cfg (e.g. mmcsd_evm.cfg, am335x_app_evmam335x.cfg and so on):

Mmu.enableMMU = true;

// Force peripheral section to be NON cacheable strongly-ordered memory
var peripheralAttrs = {
    type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
    tex: 0,
    bufferable : false,                // bufferable
    cacheable  : false,                // cacheable
    shareable  : false,                // shareable
    noexecute  : true,                 // not executable
};

// Define the base address of the 1 Meg page
// the peripheral resides in.
var peripheralBaseAddr = 0x44e00400;;

// Configure the corresponding MMU page descriptor accordingly
Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
                          peripheralBaseAddr,
                          peripheralAttrs);

                          
// Define the base address of the 1 Meg page
// the peripheral resides in.
var peripheralBaseAddr = 0x481a6000;

// Configure the corresponding MMU page descriptor accordingly
Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
                          peripheralBaseAddr,
                          peripheralAttrs);

What does this code mean?  Why is it necessary? Especially, the peripheralBaseAddr variables seem to be initialized with nonsense addresses when refering to the memory map in the AM335x TRM:

• 0x44e00400 -> CM_WKUP (inside the L4_WKUP peripheral memory map)
• 0x481a6000 -> UART3 (inside the L4_PER peripheral memory map)