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DM8148. EDMA Channel Controller 0 Configuration Registers memory map

Marat Shchuchinsky
Expert 2595 points

Hello TI' teams!
Have a small misundertsanding about DM8148 EDMA Channel Controller 0 Configuration Registers.
SPRS647E.pdf - DM8148 TRM show me 2 tables of C674x Memory Map, one when MMU enabled (EDMA TPCC registers base = 0x0900_0000) and second when MMU bypassed (EDMA TPCC registers base = 0x4900_0000).
Am I correctly understood from e2e forum and chip errata, that system MMU always enabled on DM8148 and can't be bypassed?
So ECR/ECRH and IPR/IPRH registers are accessed always by base address 0x49000000 and not by 0x09000000 as show DMA examples supplied by dvrrdk?

  • 0
    TI__Guru**** 170625 points
    Marat,

    Latest DM814x TRM is SPRUGZ8F.pdf I can not find EDMA TPCC base address there

    SPRS647E.pdf is DM814x data manual, in table 2.5 MMU Bypassed C674x DSP Memory Map I can see we have both options:

    0x0900_0000 - EDMA Channel Controller 0 Configuration Registers

    0x4900_0000 - EDMA Channel Controller Registers

    BR
    Pavel
  • 0 in reply to Pavel Botev
    Expert 2595 points
    Hello Pavel,
    Thanks a lot for your reply. I don't clearly understood, what means "MMU disabled". How I can to check the MMU status on alive system for use correct address for apply to EDMA Channel Controller registers?
  • 0 in reply to Marat Shchuchinsky
    TI__Guru**** 170625 points

    The base address of the EDMA registers (physical address) is 0x49000000.

    If you are using virtual memory addresses from 674x DSP (0x09000000) please make sure this corresponds to the proper physical address.

    ti-ezsdk_dm814x-evm_5_05_02_00/component-sources/edma3lld_02_11_05_02/packages/ti/sdo/edma3/drv/sample/src/platforms/sample_ti814x_cfg.c

    /**

    * \brief Base address as seen from the different cores may be different

    * And is defined based on the core

    */

    #ifdef BUILD_CENTAURUS_DSP

    #define EDMA3_CC_BASE_ADDR                          ((void *)(0x09000000))

    #define EDMA3_TC0_BASE_ADDR                          ((void *)(0x09800000))

    #define EDMA3_TC1_BASE_ADDR                          ((void *)(0x09900000))

    #define EDMA3_TC2_BASE_ADDR                          ((void *)(0x09A00000))

    #define EDMA3_TC3_BASE_ADDR                          ((void *)(0x09B00000))

    #else

    #define EDMA3_CC_BASE_ADDR                          ((void *)(0x49000000))

    #define EDMA3_TC0_BASE_ADDR                          ((void *)(0x49800000))

    #define EDMA3_TC1_BASE_ADDR                          ((void *)(0x49900000))

    #define EDMA3_TC2_BASE_ADDR                          ((void *)(0x49A00000))

    #define EDMA3_TC3_BASE_ADDR                          ((void *)(0x49B00000))

    #endif

    See also the below pointers:

    Regarding MMU, refer to the below pointers:

    BR
    Pavel