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TMS320C6670. Evaluation and custom board's problem.

Taras Kolesko
Expert 1730 points
Other Parts Discussed in Thread: TMS320C6670

Hello again.

I have the TMDSEVM6670L evaluation board and the custom board. Both having the same processor - TMS320C6670 and the same problems. I'll start from the TMDS evaluation board:

When i'm trying to reset it with the "hard reset" button and i'm pressing it just once, without pressing for a long time, the core clock is 999,98 MHz and ddr clck is 66 MHz. And when i'm holding it for a while, the ddr clock decreases to 25 MHz!! And this holds until i reset it again. The custom board with the same architecture, but without JTAG, keeps the 25 MHz value with or without reset. I haven't found the source of the problem in TMDS, hope you can help me with that. How the ddr clck depends on reset and why it is decreasing? 

  • 0
    TI__Guru* 81335 points
    Hi Taras,

    The TMDXEVM6670L has 3 push button switches and are RST_FULL1, RST_COLD1, and RST_WARM1.

    RST_FULL1 - Full Reset Event - This will issue a RESETFULL# to TMS320C6670 by the FPGA.
    RST_COLD1 - Cold Reset Event (Reserved for Future Use)
    RST_WARM1 - Warm Reset Event - This will issue a RESET# to TMS320C6670 by the FPGA.

    Please provide below information,
    1. Are you trying reset using RST_FULL1 switch?
    2. Your custom board design also has a FPGA like EVM?

    Thank you.
  • 0 in reply to Raja
    TI__Mastermind 46460 points

    Taras,

    You need to debug the problem.  Please use a scope and verify that the DDRPLL reference clock and the SYSCLK reference clock are as expected.  Measure the frequency and the single-ended voltage levels.  If these are correct, then you need to connect CCS to the processor and check the PLL programming.  The CCS GEL file contains code to properly configure the PLLs.  This GEL can also be used to program the PLLs on the custom board once you adjust the settings for your reference clock rate.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1730 points

    Hello Tom.

    I've got a few questions about debug session you described.

    First - "scope". You mean Code Composer scope or hardware oscilloscope?
    Second - "gel files". As i previously described in my past themes - i'm still working on the JTAG problem on my custom board. IE - it doesn't contain JTAG and i'm trying to make a stable connection, using TMDS. Are there any other ways to program PLLs without .gel files?

  • 0 in reply to Taras Kolesko
    TI__Mastermind 46460 points

    Taras,

    I was recommending use of an oscilloscope to measure clock signals.  It needs to be used to verify power, clock and reset sequencing as mandated in the Data Manual.

    JTAG connectivity is very basic.  If you cannot get this to work then you are wasting your time elsewhere.  You only need power, reset release, clock and 5 JTAG signals to get emulation to operate.  This needs to be your focus.  Please see: www.ti.com/lit/spru655 and processors.wiki.ti.com/index.php/XDS_Target_Connection_Guide.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1730 points
    Ok, i've finished my work with JTAG connection, thank you, links were helpful, i wasn't paying much attention to those things you described, now it's working on both boards. But i still can't understand, how to read the register values, like PLLCTL, SYSCLK and others, which specifies frequencies i needed. The values on custom and on TMDS for DSP frequency are correct, like it described here:
    pdf.icpdf.com/.../TMS320_datasheet.pdf (page 35, table 2-13)
    and both equal 999,98 MHz, but the PLLM and PLLD are different from the table for some reason. Values in the DCHANGE and PLLM are different, but i have no idea how to make them correct like on TMDS.
  • 0 in reply to Taras Kolesko
    TI__Genius 9065 points
    Hello,

    Do you have Code Composer Studio installed?

    processors.wiki.ti.com/.../Category:Code_Composer_Studio_v6
    processors.wiki.ti.com/.../Category:CCSv6_Training

    You can view memory in CCS after you configure target configuration and connect to the cores you are interested in. In memory windows, type in the memory mapped address of the registers you are interested in. Check deveice datasheet and peripheral user guide to get exact address.

    regareds,
    David
  • 0 in reply to dzhou
    Expert 1730 points
    Of course i have it installed. I don't understand how to work with memory map and what i should put in.
  • 0 in reply to dzhou
    Expert 1730 points
    F.E. - i can't find in the manuals, how the PLL frequency is calculated through the registers. According to "C66x CorePac System PLL Configuration" table, i need to know the CLKIN value. Is it defined by DIP-switches or something else? And how the values for PLLM and PLLD are determined? And the last question - i check the the registers i need, i get values, i can decrypt them with the manuals. But! I still don't understand the algorhytm, how the table "C66x CorePac System PLL Configuration" values are calculating. I think if i will understand that, i could solve my custom board problem. Can you please explain me the problem, or link to resources that would help me?
  • 0 in reply to Taras Kolesko
    TI__Mastermind 46460 points

    Taras,

    There are example routines in the GEL file provided with CCS for the C6670 EVM.  It is probably located in C:\ti\ccsv5\ccs_base\emulation\boards\evmc6670l\gel and the name is evmc6670l.gel.  CCS will find this file for you.

    The MCSDK software provided by TI also has PLL configuration routines but I recommend that you start with the GEL files for debugging your board.

    Details about the PLL configuration are found in the Data Manual (http://www.ti.com/lit/gpn/tms320c6670) and the PLL UG (http://www.ti.com/lit/pdf/sprugv2). 

    Documentation for the EVM is available at: http://www2.advantech.com/Support/TI-EVM/6670le_of.aspx.  The schematic and the technical reference will provide details about the reference clock input frequencies.  Similarly, you need to get this information from your hardware design.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1730 points
    Ok, and the last question. On the custom board i have an issue, that the power voltage for the PLL's is sometimes 1.2 V. According to datasheets and manuals, it must be 1.8 V. Can this issue affect frequency of the PLL?
  • 0 in reply to Taras Kolesko
    TI__Mastermind 46460 points

    Yes, it is important for the supply voltages to be within their rated limits at all times while the device is out of reset.  It is also important that the supplies ramp to their rated voltages in the order shown in the supply, clock and reset sequence shown in the Data Manual.

    Tom