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66AK2L06 JESD Attach to ADC12J4000/DAC38J84 throughput

Matt Verber
Prodigy 110 points
Other Parts Discussed in Thread: DAC38J84, 66AK2L06, ADC12J4000

I'm considering using the "66AK2L06 JESD Attach to ADC12J4000/DAC38J84" development kit for a project, but I need to understand its data throughput.  Basically, I want to read samples from the ADC as quickly as possible, perform some simple computations on the samples, and then output the result to the DAC.  I understand the DFE can operate in bypass mode to dump the samples to IQN2, which then copies the samples to memory for processing, but how can I determine the overall system throughput rate?

Essentially, I need to understand if any bottlenecks exist in the processing chain.  I'd like to see a test where, for example, samples are read from the ADC, 5 samples are summed, and the result is written to the DAC.  What's the fastest real-time rate that can be sustained?

  • 0
    TI__Guru* 81335 points

    Welcome to the TI Keystone E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • 0
    TI__Mastermind 37500 points

    Hello,

     

    The demo1, uses the signal processing to combine 2 Tx Axcs, into 1 Tx stream.   The reverse process is also done 1 Rx stream, split into 2 Rx Axcs.  This is described below.  Also if 1 Tx Axc -> 1 Tx stream, after this there is a discussion of 1 Axc -> 1 stream with an IQ rate of 122.88Msps.  You would need to discuss your application with the local TI FAE, as this is a customized version.

    The demo #1 processing takes two channels from BBTx to a summed 368.64Msps rate, to one Tx stream, depending on the JESD Tx byte clock, the Tx data is resampled To the output rate:

     

         Tx side, BBTx0 -> PFIR filter, Res bypassed, CIC bypassed, NCO bypassed, SumCh to Stream 0,

         bypass CFR (to reduce latency), CDFR interp4,  Mix to -43Mhz, Sum to Tx0 ->

                        BBTx1 -> same processing as BBTx0,  Mix to 43Mhz,  Sum to Tx0 ->

         -> byp DPD, Tx output Tx0, JESD parIQ (368.64Msps), 2 lane JESD Tx 7.3728Gbps

     

         Rx side 2 lane JESD Rx 7.3728Gbps -> JESD parIQ (368.64) -> Rx IF Tune 43Mhz, dec2 -> Rx (184.32)

             -> RxDDUC NCO byp, CIC byp, Res byp, PFIR dec2 -> 92.16Msps BBRx0

              similar process for BBRx1, Fdbk IF Tune -43Mhz, dec2 -> Fdbk(184.32) -> BBRx1

     

    Demo # 1 performs signal processing tasks.  Modified to your description, a single channel/stream version is not tested yet with JESD bypass.  The signal processing delay would be lower.

    1 stream / 1 Axc processing is 122.88Msps.

     

    In order to have more than 1 stream, or output formats other than interleaved IQ, a signal processing bypass is needed (not the same as JESD bypass).

     

    The bypass function requires a single JESD lane, so at the highest single channel rate and the BBRx rate must match the signal rate.  (not tested yet)

         Rx (single stream, single BBRx)

               ADC complex output rate is 122.88Msps complex, transported as interleaved IQ over 1 JESD lane.  JESD byte clock 245.76Mhz, x20 4.9152G Line rate

               JESD bypass, formatted in BBRx to the 4 sets of 16bit IQ for AID transport

         Tx (single stream, single BBTx)

                AID input 1 Axc, 122.88Msps – translated to interleaved IQ 245.76Mhz, JESD bypass , output is 1 JESD lane in interleaved IQ, JESD byte clock 245.76Mhz, x20 4.9152G Line rate  

                

    Regards,

    Joe Quintal