I/O and memory access across SoCs via Hyperlink

Mahantesh Kothiwale

Dear Experts,

We have a design case, where 2 K2K SoCs are connected over Hyperlink.

I am trying to understand from Hyperlink document, how a line of code running on ARM core or DSP core can access the I/O peripheral (Memory mapped registers) and DDR3 RAM on another SoC via Hyperlink..?

Can the 40-bit address space be divided into two parts ..? (One part for each SoC)..

Do TeraNet bus decode some MSBs of 40 bit address to pass the transaction over Hyperlink ..?

Please point me to the right document explaining the address mapping across 2 SoCs connected over Hyperlink ..

Also, please let me know the CCS tool-chain support to define 64 bit pointers to hold 40 bit addresses and necessary linker scripting to locate the particular data and code segments to the addresses mapped to SoC1 and SoC2.

Thanks,

Mahantesh.

over 9 years ago

0 Ganapathi Dhandapani95 over 9 years ago

TI__Mastermind 28085 points

Hi,

Please take a look at Keystone Hyperlink user guide document, it will help you to understand the Memory mapping between two SOC.

Also refer the below Hyperlink training link:

TI has provide Hyperlink example code in MCSDK package, please refer this example code to understand the code flow.

MCSDK Path: C:\ti\pdk_keystone2_3_01_04_07\packages\exampleProjects\hyplnk_K2KC66BiosExampleProject

For my understanding, CCS tool-chain does not support to define 64 bit pointers. Refer attached MPAX register example code to access the 40-bit address and refer keystone lab manual document to running MCSDK Hyperlink example and MPAX example.

MPAX_registersDemo.zip

Thanks,

0 Mahantesh Kothiwale over 9 years ago in reply to Ganapathi Dhandapani95

Prodigy 200 points

Dear Ganapathi,

Thank you! The links provided give enough insight on Hyperlink.

Regards,

Mahantesh.

Processors

Processors forum

I/O and memory access across SoCs via Hyperlink