DM8127 UBoot changes

Hello,

I will notify the IPNC team for help.

BR
Margarita

Hi JK,

Regarding DDR3 u-boot modifications, refer to the below wiki:

processors.wiki.ti.com/.../EZSDK_Memory_Map
processors.wiki.ti.com/.../TI814x-DDR3-Init-U-Boot

Regarding DDR3 size report message modification, refer to the below patch:

arago-project.org/.../

BR
Pavel

Hi,

For the 256 MB DDR on DM8127 you should modify the DMM LISA mapping accordingly in the '..\ti_tools\ipnc_psp_arago\u-boot\arch\arm\include\asm\arch\ddr_defs_ti814x.h' file:

The default configuration is for 1 GB DDR:

/*
* TI814X PG2.1 DMM LISA MAPPING
* 1G contiguous section with 128-byte interleaving
*/
#define PG2_1_DMM_LISA_MAP__0 0x0
#define PG2_1_DMM_LISA_MAP__1 0x0
#define PG2_1_DMM_LISA_MAP__2 0x805C0300
#define PG2_1_DMM_LISA_MAP__3 0xA05C0300

regards,
Anand

Hi Anand,

Thanks  for the reply. Have  a question  about the  beginning address. How  do I choose  it ?

For  example:

#define PG2_1_DMM_LISA_MAP__0 0x0
#define PG2_1_DMM_LISA_MAP__1 0x0
#define PG2_1_DMM_LISA_MAP__2 0x805C0300
#define PG2_1_DMM_LISA_MAP__3 0x905C0300

Will  this  work ?

Another  question:  Which file need to be modified  for DM388   ? The same \ddr_defs_ti814x.h ?

Best regards

JK

Hi,

The page size on the M3 MMU is 512 MB (..\ipnc_rdk\ipnc_mcfw\mcfw\src_bios6\cfg\ti810x\AMMU_m3.cfg), the first page is from 0x80000000 to 0x9FFFFFFF which is cached and the second page is from 0xA0000000 to 0xCFFFFFFF.

So accordingly for 256 MB your second 126 MB should start from 0xA0000000.

Yes, the same file is applicable for DM388.

regards,

Anand

Hi Anand
I am not clear on the address 0x805C0300. How do we get this address ? (In #define PG2_1_DMM_LISA_MAP__2 0x805C0300).
If we add 256MB to this address, we get 0x905C0300. I know only this.

Best regards
JK

Hi,

On DM8127 there are 2 EMIF so there is interleaving of the physical address space.
And for your 256 MB memory map you are going to connect 128 MB DDR3 chips to each of the EMIFs.

The 256 MB memory map should be divided into 2 halves of 128 MB as follows:

First 128 MB       : 0x80000000 to 0x88000000 -> cached on A8 and M3
Second 128 MB : 0xA0000000 to 0xA8000000 -> since for M3 MMU second 512 MB page starts at 0xA0000000

Accordingly the DMM LISA MAP will be:

MAP_0 :

SYS_ADDR     = 0x80 -> MSB
SYS_SIZE        = 0x03 -> 128 MB section
SDRC_INTL    = 0x03 -> 512 byte interleaving
SDRC_MAP    = 0x03 -> Mapped on SDRC0 and SDRC1 (interleaved)
SDRC_ADDR = 0x00 -> MSB

          = 0x803C0300

MAP_1 :

SYS_ADDR     = 0xA0 -> MSB
SYS_SIZE        = 0x03 -> 128 MB section
SDRC_INTL    = 0x03 -> 512 byte interleaving
SDRC_MAP    = 0x03 -> Mapped on SDRC0 and SDRC1 (interleaved)
SDRC_ADDR = 0x04 -> MSB,64 MB on each DDR3 chip

          = 0xA03C0304

regards,
Anand

Hi,

I just figured out that the 'NOTIFY_SHARED_ADDR' in the memory map (..\ipnc_rdk\ipnc_mcfw\mcfw\src_bios6\cfg\ti814x\config_256M.bld) should match with the notifyk.vpssm3_sva=0xBFD00000 in the boot args.

So you should use the lower 128 MB of the second 512 MB page.

So second 128 MB will start from 0xB8000000.

Accordingly:

MAP_1 :

SYS_ADDR     = 0xB8 -> MSB
SYS_SIZE        = 0x03 -> 128 MB section
SDRC_INTL    = 0x03 -> 512 byte interleaving
SDRC_MAP    = 0x03 -> Mapped on SDRC0 and SDRC1 (interleaved)
SDRC_ADDR = 0x04 -> MSB,64 MB on each DDR3 chip

 = 0xB83C0304

 

regards,

Anand

Thanks Anand. I will build the image and flash. Will let you know the results.

Best regards
JK