Using PLL1_SYSCLK2 as source for ASYNC3

jw7

I am using a C6748 DSP. I would like to use PLL1_SYSCLK2 as the source for the ASYNC3 clock domain however, when I switch ASYNC3 to use this clock, I get a processor stall whenever I try to access any of the peripherals in the ASYNC3 clock domain (SPI1, ECAPx, etc.). The peripherals can be accessed fine when I leave the ASYNC3 clock source set to the default source PLL0_SYSCLK2. I know that PLL1 is working because I can access my mDDR memory.

over 9 years ago

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

What software package are you using ?
Is it your own code or TI examples ?

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

I have tried to run UART2 (ASYNC3 domain) starterware echo example with PLL1_SYSCLK2 (CFGCHIP3.ASYNC3_CLKSRC) and didn't get any problem.

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Hello,

Could you please ensure that you change the CFGCHIP3.ASYNC3_CLKSRC bit to 1 to source PLL1_SYSCLK2 to AYNC3 domain ?

Regards,
Senthil

0 jw7 over 9 years ago in reply to Senthilkumar Srinivasan

Intellectual 255 points

That bit is being set correctly, but I traced the problem to the enable bit of PLL1.SYSCLK2 divider enable bit not being set. It defaults to off and that makes some sense, since PLL1.SYSCLK2 does not drive anything by default. With it set, the ASYNC3 clock domain peripherals work for either setting of CFGCHIP3.ASYNC3_CLKSRC as expected. Thanks!

0 Senthilkumar Srinivasan over 9 years ago in reply to jw7

TI__Mastermind 43660 points

Thanks for the update.

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Using PLL1_SYSCLK2 as source for ASYNC3