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[C6655, PCIe] Physical AC timing specifications are available ?

Naoki Kawada
Guru 19890 points

Hello,

One of my customer is asking me whether or not physical AC timing specifications for PCIe, especially for data lines are available.

I know there are some timing requirements for clock lines in datasheet but there is no spec for data line. And I believe the only thing users have to do is following the guideline described in HW design guide and SerDes implementation guide when building their target board. IBIS-AMI model for PCIe would help for the simulation. Is my understanding correct ? Or, are there any timing spec descriptions in PCIe specification manual ? Unfortunately, I'm not PCI-SIG member so I don't know well about PCIe specification manual... Could you please suggest me how we can handle the requests like this ?

Best Regards,
Naoki Kawada

  • 0
    TI__Mastermind 43660 points
    Hello Naoki,

    The most important guidelines on the data line are trace impedance, length matching between P and N lines and minimum spacing to avoid crosstalk. I think all these parameters would be covered if you follow the guidelines described in the HW design guide document. In addition to that, performing SI simulation using IBIS-AMI model also would be helpful to verify your design. You may also refer electrical specification in the PCI Express Base Specification document for more details. It should be available online.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    TI__Guru**** 176811 points

    Kawada-san

    There is AC Timing Specification for reference clock. You can point the customer to chapter 4 of the PCIe specification on the TX and RX specification.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Guru 19890 points

    Hello Senthil and David,

    Thanks for your reply. Sorry to ask you so much, but now next question raised. That is about DC spec of C6655 PCIe differential signals.
    They are using PCIe and trying to observe actual waveform to verify that the actual waveform has enough margin to latch incoming data.
    They need some DC specifications on C6657 such like:

    • Allowed max input voltage
    • Minimum differences between differential signals to latch the incoming data
    • etc...

    Is it possible for you to provide such information ?
    If not possible, what is the proposal to verify the signal quality ?

    Best Regards,
    Naoki Kawada

  • 0 in reply to Naoki Kawada
    TI__Guru**** 176811 points
    Kawada-san

    I would refer them to chapter 4 of the PCIe spec for the TX and RX DC spec. They need to run full PCIe compliance test to ensure TX and RX signal quality.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Guru 19890 points
    Hello David,

    Hmm.. Ok, let me talk with the customer next week, but please let me confirm one thing. Can I understand TI has verified PCIe functionality with 'qualified' waveform which follows the spec sheet ? If the actual waveform meets the requirements described in the spec sheet on their target board, does it mean the waveform itself should be regarded as 'qualified' ?

    Best Regards,
    Naoki
  • 0 in reply to Naoki Kawada
    TI__Guru**** 176811 points
    Kawada-san

    It's not the waveform that is qualified, the compliance tests ensure the system (system includes clocking, device, trace routing, etc) under the test meets the PCIe spec using certain waveform. If you are able to fully pass the compliance test, then there is a good chance that the system will work with other PCIe products.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Guru 19890 points
    Hello David,

    Today I talked with customer and they understood your answers. Thanks for your helps.

    Best Regards,
    Naoki