UPP on C6748 and UORQ error

lavenu patrick1

Hello,

I'm using UPP on C6748. My UPP is working at 50 Mhz in transmit mode with Q Channel . I configured the UPP_TX_CLKSRC in CFGCHIP3 to use the external signal 2xTXCLK.

I have a test that is sending data at very slow rate on UPP : 6 bytes every second.

When I run my test, i noticed that sometimes , the UORQ event rised. It is very strange because the CPU is not overloaded and only reserved for my test.

When the UORQ event rised and If I ignore it , the test continue to work without resetting the UPP. It looks like this event has no impact on the UPP.

I noticed that also if I change the UPP_TX_CLKSRC to an internal clock (PLL1_SYSCLK2 for example) I have no UORQ error.

Could someone explain me what is happening ? could a "bad" external clock for UPP_TX_CLKSRC generate an UORQ error ?

Thank you very much for your help.

regards

Pat.

over 10 years ago

0 Sivaraj Kuppuraj over 10 years ago

TI__Mastermind 35645 points

Hi,

We will work on your request and will get back to you as soon as possible.

Thanks & regards,
Sivaraj K

0 Titusrathinaraj Stalin over 10 years ago

TI__Guru** 116100 points

Dear Lavenu,
What frequency are you driving to the 2xTXCLK ? 50MHz ?

Please refer to the following posts.
e2e.ti.com/.../107588
e2e.ti.com/.../903390

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

patrick,

The external clock 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate as it is is divided down by 2 inside the uPP. So please ensure this on your design. You could refer Table 6.116 in device data manual for 2xTCLK timing requirements.

Also a bad quality external clock might trigger the UORQ error. So i suggest you to ensure the quality of the external clock.

I believe the above posted threads would be very helpful to understand the UORQ error in relation to 2xTXCLK.

Regards,
Senthil

0 lavenu patrick1 over 10 years ago in reply to Titusrathinaraj Stalin

Intellectual 600 points

Hello,

Thank you very much for your suggestions, my external clock is 100 Mhz so the 2xTXCLK is at 50 Mhz.

regards,

pat.

0 lavenu patrick1 over 10 years ago in reply to Senthilkumar Srinivasan

Intellectual 600 points

Hello Senthil,

Thank you very much for your help and suggestions. i confirm you that my external clock is at 100 Mhz and so the 2xTXCLK at 50Mhz.
Please you made a reference to the table 6.116, please could you tell me where I can found it ? in which document ? I didn't find it in sprugj5b , thank you very much.

regards,

Pat.

0 Senthilkumar Srinivasan over 10 years ago in reply to lavenu patrick1

TI__Mastermind 43660 points

Patrick,

Please refer C6748 data manual SPRS590F for the timing requirements. If possible please share the scope capture of the 2TxCLK to verify its quality.

Regards,
Senthil

0 lavenu patrick1 over 10 years ago in reply to Senthilkumar Srinivasan

Intellectual 600 points

Thank you very much for your answer Senthil, I'm going to check the timing.

Best regards,

Pat.

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UPP on C6748 and UORQ error