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ECC problem with 16bit NAND flash and EDMA3

xxx xxx93
Prodigy 30 points
Other Parts Discussed in Thread: OMAPL138, OMAP-L138

Hi,

we own a custom board with OMAPL138BZWT CPU with a 16bit NAND flash attached on EMIFA CS2. We had a working NAND flash / EDMA3 configuration for reading NAND as follows which we also used on OMAPL138LCDK for development.

We are using EDMA3_1 TC0 using QDMA.

In the data phase, while the ECC hw is active (between phases 1 and 3 of SPRUH77A in 'reads' section) the EDMA is configured as follows:

ACNT = 2

BCNT = 512 / 2

CCNT = 1

SBIDX=0

DBIDX=2

however, under this configuration the EMIF interface does not make read bursts on EMIFA interface (1 CE pulse / 1 read cycle).

We noticed that to enable bursts, we have to set SBIDX=ACNT, this way EDMA3 optimization on transfer will occur as staten in the EDMA3 documentation.

Under this new configuration we see 8 read pulses for every 1 CE cycle with a bandwidth good enough for our application. The problem is that with this new configuration (which only changes SBIDX) the ECC hardware always returns a syndrome value != 0 (ECC error indication). Where is the problem? Are there any issues related with 16 bit NAND flash or by this configuration?

Best regards,

Luca

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    I don't think, this would be a EDMA configuration issue. What is the calculated 4-bit ECC error addresses "NANDERRADDx" and as well the calculated 4-bit ECC error values "NANDERRVALx". I would suggest you to check the NAND Flash 4-bit ECC load register "NAND4BITECCLOAD" to evaluate the status of 4-bit ECC load value it takes in the load register since this is the value which is used to load the ECC values when performing the Syndrome calculation during reads. This should be a error indication related to ECC load syndrome calculation performing some mess up. Kindly refer section 20.4.15 from spruh77a doc. below:

    http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

    Thanks & regards,

    Sivaraj K

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  • 0
    TI__Guru** 116100 points
    Dear Luca,
    Can you please try to use the following example which uses EDMA3 + NAND16.

    C:\ti\OMAPL138_StarterWare_1_10_04_01\examples\lcdkOMAPL138\nand

    C:\ti\OMAPL138_StarterWare_1_10_04_01\nandlib\nand_emifa2.c
  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 30 points
    Hi Sivaraj,

    Thanks for your support.

    After many tests I found the solution of the problem. To get the best transfert performance I configured the EMIFA CEnCFG register with minimum read access cycles ( R_SETUP = 0 [11ns], R_STROBE = 1 [22ns], R_HOLD = 0 [11ns] when EMIFA clock = 91 MHz ) and it worked well with the NAND Flash we have ( no wrong data on reading the NAND by EDMA controller ). When burst mode is enabled the read accesses are closer together and this is not a problem for the nand transfert itself, BUT it produces a problem for ECC procedure. It is enough to increase the hold time of the read access to make the ECC work correctly ( R_HOLD = 1 ). Arghhh, I've just seen that there is a note in the SYS_CLK_CALC_OMAP-L138 Excel file which say: "For reliable 16-bit NAND operations R_HOLD must be set to 1 to ensure 2 clock cycles for ECC calculation". Yes, of course it would be helpful to have this note even in the OMAP L-138 Technical Reference Manual....

    Regards,
    Luca
  • 0 in reply to xxx xxx93
    TI__Mastermind 35645 points
    Hi,

    Thanks for your update. Glad that you have found the solution and we would appreciate your recommended note to have it in the TRM as well.

    We proactively appreciate your contribution since the solution you proposed above which would help other E2E community member as well.

    Thanks once again.

    Regards,
    Sivaraj K
  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 30 points
    Hi Titus,
    Thanks for your reference.
    I tried the StarterWare example about nand by edma. It works but I think it doesn't initialize EMIFA properly, because I find CEnCFG register with default values regarding R_SETUP, R_STROBE and R_HOLD fields. Fortunately I figured out the problem, that is in the minimum R_HOLD setup that 16-bit nand imposes for correct ECC calculation ( R_HOLD > = 1 for 16-bit nand flash ).

    Best Regards,
    Luca
  • 0 in reply to xxx xxx93
    TI__Guru** 116100 points
    Dear Luca,
    Sounds good.
    Thanks for your update.