AM572x Processor Selection

Hi Biser Gatchev,

For instance, in the AM572x technical reference manual, the ethernet frame size refers to 2016 Bytes. All 10/100/1000 Ethernet controller supports this frame size, but for Jumbo packets feature, it has to be between 1500 and 1900 Bytes. Also, in technical reference manual, could not find chapter describing Crypto IP.

Request to address each of the feature/support in AM572x.

Also please give reference to Linux BSP documents which describes the following

• Boot Modes
• Linux Driver Reference and Usermanuals
• Binary (Uboot, uIMage and File system) upgrade method from different source like SD, eMMC, NAND Flash, Ethernet.....

Thanks & Regards,

Madhu

Madhusudhan Seshadri said:

For instance, in the AM572x technical reference manual, the ethernet frame size refers to 2016 Bytes. All 10/100/1000 Ethernet controller supports this frame size, but for Jumbo packets feature, it has to be between 1500 and 1900 Bytes.

Jumbo frames can be up to 9000bytes long. Please see this thread for an explanation: https://e2e.ti.com/support/arm/sitara_arm/f/791/t/461724 Same applies for AM57X.

Madhusudhan Seshadri said:

Also, in technical reference manual, could not find chapter describing Crypto IP.

This is only provided under NDA, that's why I asked you to contact TI directly.

Madhusudhan Seshadri said:

Boot Modes

See section 33 of the AM57X Technical Reference Manuals.

Madhusudhan Seshadri said:

• Linux Driver Reference and Usermanuals
• Binary (Uboot, uIMage and File system) upgrade method from different source like SD, eMMC, NAND Flash, Ethernet.....

There are a lot of materials on the wiki, you can start from here: http://processors.wiki.ti.com/index.php/Sitara_Linux_Software_Developer%E2%80%99s_Guide

Hello Madhu,

In addition to Biser's post:

Boot Mode Requirement :

SPI flash (with kernel and rootfs located in eMMC). This to be considered the normal, deployed case

The device allows booting from eMMC embedded memories or SD cards connected to device embedded MMC2 or MMC1 controllers I/Os, respectively. The booting interface is selected by configuration of the SYSBOOT pins.

SPI flash (with kernel loaded via TFTP and NFS root file system)

SPI/QSPI Flash memories provide a storage solution for systems with limited space, pins and power. The ROM code support for SPI/QSPI devices has the following characteristics:

• 24-bit addressing, up to 128 Mbit (16 MiB), no banking

• QSPI1 on CS0 is the communication interface

UART boot (Disaster recovery)

- The ROM code can boot from these peripherals:

• USB1: High-, and Full-speed USB from USB1 internal transceivers

• UART3: 115.2 Kbps, 8 bits, even parity, 1 stop-bit, no flow control

Initialization Phase for UART Boot The ROM code supports booting from a UART interface with the following characteristics:

• UART3 interface

• Communication parameters set to 115.2 Kbps, 8 bits, even parity, 1 stop-bit, no flow control

• Two-pin interface: RX/TX

• The boot message default time-out is 300 ms (time-out boot message)

About AM572x software please see the guide - processors.wiki.ti.com/index.php

Ethernet Requirement:

Jumbo frame support

IP/UDP/TCP checksum offloading

Hardware buffer management

How many Giga bit(1000Mbps) and 10/100 Mbps Ethernet port supported in various sub-systems(ARM, DSP, PRU-ICSS...)

 - Two Ethernet ports (port 1 and port 2) with selectable RGMII, RMII, and G/MII (in MII mode only) interfaces plus internal Communications Port Programming Interface (CPPI 3.1) on port 0 • Synchronous 10/100/1000 Mbit operation

The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device.

What is its performance parameter of all ethernet ports?

Real-Time(RT) Patch: The Linux kernel used in the BSP is a Real-Time kernel, with RT patch applied

If RT patch is applied in Linux Kernel, whether following performance can be achieved

Ethernet packet arrival jitter within 50us in user space

Ethernet latency within 100us in user space

See the GMAC switch latency, there is no information about Ethernet latency in user space:

Crypto Engine:

Please provide more detailed documentation for Crypto Engine features and capabilities.

Whether Linux BSP supports this feature?

Will this be available as Library APIs for application development?

- For more about Crypto accelerators, please contact your FAE.

AM572x supports following modules available in table 3-27 in device TRM:

PCIe:

Number of Lanes supported in PCIe.

The PCIe controller is capable to operate either in Root Complex (RC) or in End Point (EP) PCIe mode. The device PCIe_SS1 controller supports up to two 16-bit data lanes on its PIPE port. The device PCIe_SS2 controller supports only one 16-bit data lane on its PIPE port.

Field Upgrade:

Whether remote update of UBoot, Kernel and File system is supported in BSP

And is it possible to upgrade through USB and Ethernet

- Yes, this feature is supported by AM572x, for more information contact your FAE.

Best regards,

Yanko