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TCI6630K2L Predistorter architecture and DFE sampling rates

Michael Fauth
Prodigy 70 points

Hi all,

I am currenty evaluating the K2L SoC. I am wondering what kind of predistorter architecture is implemented within the DPD block. The DFE Userguide says something about LUTs and memory taps, but there is no detailed description available. For example, i was not able to find a register descrition.

Another question is about the DFE in general: Is it possible to choose the sampling rates independent for the RX and TX path?

Thanks,

Michael

  • 0
    TI__Guru* 81335 points

    Hi Michael,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • 0 in reply to Raja
    TI__Mastermind 37500 points
    Hello,
    The DPD block predistorter is typically implemented as a hardware component, and a software adaption component. The register definition is not directly accessible. Within the MCSDK, under the DFELLD there is a CSL, and functional definition of what is supported in the software. The hardware component has a method to map, delay, sum 36 Lookup Tables' outputs into multiple antenna streams, and multiple cross term distorters. The Lookup tables can index the magnitude or magnitude squared of the signal, and depending on the mapping and adaption provide the 1/G response to a selected subset of the Volterra solution selected.

    The Tx and Rx sampling rates can be different, however in the common Serdes blocks 2-0 (lanes 0,1) and Serdes blocks 2-1 (lanes 2,3) the byte clock (actually word clock) data rate must be the same if the Tx and Rx share the serdes. Typical Tx sampling rates are 61.44, 92.16,122.88, 184.32 (1,2, or 4 stream), 245.76, 368.64 (1 or 2 stream). Typical Rx sampling rates are 61.44, 92.16 (1,2,4 stream), 122.88, 184.32 (1,2 stream), 245.76, 368.64Msps (1 stream, 2 stream [special setup]).

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Prodigy 70 points
    Joe,

    thanks for your response. Regarding the DPD: I know about the DFELLD and its functions. But it is really hard to understand what actually is covered by the software without knowing the hardware implementation of the predistorter. Is there a block diagram of the predistorter available? (I know the block diagram from the DFE Userguide - one with more details would be nice) .

    Or maybe a paper that descibes what is going on there?

    Let's pick for example the function DFE_Err Dfe_progDpdLutTable( DFE_Handle hDfe, uint32_t blkId, uint32_t rowId, uint32_t cellId, DFE_DpdData * DpdData ):

    I understand what the DFE_Handle parameter is for. But how do i know what blkId i need? I don't even understand what the block ID exactly is. The same applys for the other parameters of the function. Especially for the DpdData parameter. What does lutGain and lutSlope mean? How do theres values influence the transfer function of the predistorter?

    From what i know at the moment, my guess is that the hardware does some kind of memory polynomial implementation in which the polynomial transfer function is implemented within LUTs, and a number of luts are connected to represent the memory of the system. Is this correct?

    Do i need a special set of register programming (tgtData.c) to configure the DPD for a speciall use case?

    Greetings,
    Michael