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DDR Hardware Levelling Issue on AM5728 after warm reset

Abhiroop Boggavarapu
Prodigy 235 points
Other Parts Discussed in Thread: AM5728

By default in PSDK 02.00.00.00, the read-write levelling of EMIF Controller is done by processor itself i.e. DDR hardware levelling feature is used. When we tried to use the same feature, i.e.DDR hardware levelling, on our custom board based on AM5728, the board hangs after a reboot (warm reset) using SPI Flash as a permanent boot-device (i.e. MLO and U-boot flashed on SPI flash).  But the same board, up on cold reset reads the binaries from SPI Flash and boots fine.

During warm reset when the issue happens, on further debugging, it is found that the data present on DDR changes after some time, i.e. the data written to DDR after the DDR clocks have been re-initialised is not same when read back after a while. Is there any issue with DDR hardware levelling feature on AM5728 processor?

I have also seen the Errata of AM5728 (Link) and see that there are two below mentioned issues w.r.t Warm reset. Are these issues also relate to DDR hardware levelling issue?

i727: Refresh Rate Issue after Warm Reset
i729: DDR Access Hang after Warm Reset

Regards,
Abhiroop Boggavarapu

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will ask the AM57x team to comment on this.
  • 0
    TI__Mastermind 29520 points
    Hello Abhiroop,

    HW leveling is enabled for all AM57xx devices – all GEL packages support HW leveling by default.

    I can only assume for behavior of your board. Please provide us log with errors from DDR initialization.
    Your issues may caused by:
    User tries EMIF configuration after running some code. This causes HW leveling failure due to following reasons
    a. EMIF may not be in clean state
    b. Some cores are still trying to access EMIF

    Best regards,
    Yanko
  • 0 in reply to Yanko Todorov-XID
    Prodigy 235 points

    Hi Yanko,

    I do not see any errors from DDR initialization.Hence I am not providing any logs. We read u-boot from SPI Flash at the MLO stage and added code to calculate the CRC of the U-Boot binary and then boot to MLO (SPL). This is to ensure that the board boots reliably. I see that the calculated CRC of the downloaded image does not match with the header and this happens only on warm reset. After a cold reset, this issue is not seen. Hence I do not think that the issue is with binary on the SPI Flash.

    When you say that the issue can be seen

    If User tries EMIF configuration after running some code. 
                       - Since the same MLO code is running after a cold reset also, could this issue occur because of this?

    a. EMIF may not be in clean state
                        - What can be done to ensure that the EMIF is in clean state?

    b. Some cores are still trying to access EMIF
                      - Since this issue is seen at MLO stage, I dont think there is any other core which is active other than the master A15 core.

    Thanks & Regards,
    Abhiroop

  • 0
    TI__Guru*** 125430 points

    Abhiroop Boggavarapu said:
    During warm reset when the issue happens

    Warm reset is not allowed.  Please see i862 "Reset Should Use PORz".