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Question about C5517 IDLE3 Example in C55XCSL C5517 AUXPACK

rperezti
Genius 12710 points


I'm running through the IDLE3 example in "C55XCSL C5517 AUXPACK " Package from this link - CSL, and I have a question about the procedure.  I am able to verify ~500uA CVdd current when the device enters IDLE3 mode.  I have copied below the procedure from the readme file for reference.  My question is what is the purpose of the "pause and resume" in Step 4, and more importantly, how does one implement this step in a real embedded system that does not have JTAG control of the CPU.

Thanks.

POWER - IDLE3 RECOVERY USING RTC ALARM

TEST DESCRIPTION:
 This test configures RTC for generating an alarm 8s after it's
started, during which period the system is put into IDLE3 state. The
subsequent RTC alarm interrupt should bring the CPU out of the IDLE3
state and resume execution from where it was before it idled out.

TEST PROCEDURE AND EXPECTED RESULT:
 1. Ensure JP10 CLKSEL is shorted so that usb osc is not used.
 2. Run the test. The RTC alarm (expected after approx. 30s) would be set.
 3. Test will stop once usb clk is shut off.
 4. Pause and Resume the test.
 5. The test will execute the idle instsrn that will idle the cpu and wait for the alarm.
 6. Observe if the alarm interrupt got the CPU out of idle state.
 

  • 0
    TI__Genius 12575 points

    Hi,

    The following line in the CSL example is what is making it to pause and resume.

    CSL_USB_REGS->FADDR_POWER |= CSL_USB_FADDR_POWER_SUSPENDM_MASK; If the USB peripheral is already powered ON then pause and resume is not required.

    The above line (USB Suspend configuration) seems to  be redundant and can be commented out, This configuration needs to be controlled through USB HOST. In the subsequent CSL package release this will be taken care.

    Hope this information helps.

    Regards

    Vasanth