C665x SRIO SYS_CLK Selection

Sei Kato

Hi Travis or other expertise,

I'm looking into the SRIO configuration on C6657/6655, and I need some clarifications on SYS_CLK selection.

Travis said that there is an undocumented register bit or SYS_CLK selection in the following thread.
https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/282116/992518

Bit 9 of RIO_PER_SET_CNTL1 controls this as the following:

‘0’ => Used SYS_CLK_SEL to define the clock source SYS_CLK

‘1’ => Use vbusp_clk as the clock source for SYS_CLK

Again, this bit is only valid on rev2.0 silicon and reserved otherwise.

I believe this undocumented register bit is valid on C665x silicon rev1.0 as well as C667x silicon rev2.0 - right ?

Thanks,
Sei Kato

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

This register bit is only valid on c66xx silicon rev2.0 and reserved otherwise.

Thanks,

0 Sei Kato over 10 years ago in reply to Ganapathi Dhandapani95

Prodigy 180 points

Hi Ganapathi,

As long as I know, rev1.0 is the latest silicon rev for C6657/6655, while rev2.0 for C6678/6674.

I also read through SPRZ334H C6678 Silicon Errata and SPRZ381B C6657 Silicon Errata, and it seems the SRIO related issues found on C6678 rev1.0 are not found on C6657 rev1.0, and only the issues found on C6678 rev2.0 are found on C6657 rev1.0. This implies the SRIO on C6657 rev1.0 is almost equivalent to C6678 rev2.0, that's why I guess that register bit is valid on C6657 rev1.0.

I also tried to access that register bit on C6657EVM, and could successfully set/unset it, but I would like to know whether it works or not by design.

Thanks,
Sei Kato

0 dzhou over 10 years ago in reply to Sei Kato

TI__Genius 9065 points

Hello Sei,

Yes, you are right, the mentioned register bit is indeed valid on C6657 device.

regards,

David

0 Sei Kato over 10 years ago in reply to dzhou

Prodigy 180 points

Thank you, David.

Now it's clear to me.

Sei Kato

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C665x SRIO SYS_CLK Selection