Hi Team,
I am using CCS5.5 and calculating worst case execution time when all cores access MSMCSRAM in C6678 controller.
Test details:
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I am using SYS/BIOS and used the following code for invalidating the cache.
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#include "stdio.h"
#include <ti/sysbios/family/C66/Cache.h>
#include <c6x.h>
int ch1,ch2;
#define core_num 0
#define MPAXL2 0x08000010
#define MPAXH2 0x08000014
void main()
{
volatile int *ptr;
volatile unsigned int * mpaxl2 = (volatile unsigned int *)MPAXL2;
volatile unsigned int * mpaxh2 = (volatile unsigned int *)MPAXH2;
unsigned int st_bef[50]={0};
unsigned int st_aft[50]={0};
unsigned int value;
int i = 0;
Cache_Size *size;
Cache_getSize(size);
printf("cache sizes are 0x%x 0x%x 0x%x\n",size->l1pSize,size->l1dSize,size->l2Size);
printf("cache Modes are 0x%x 0x%x 0x%x\n",Cache_getMode(Cache_Type_L1P),Cache_getMode(Cache_Type_L1D),Cache_getMode(Cache_Type_L2));
ptr = (volatile unsigned int *)((0x0c000002) + (0x1000 *core_num));
*(mpaxh2) = (0x0c00000b + (0x1000 * core_num));
*(mpaxl2) = (0x0c0000bf + (0x1000 * core_num));
*(mpaxh2);
*(mpaxl2);
printf("0x%x 0x%x \n",*(mpaxh2),*(mpaxl2));
*(ptr) = 100;
TSCL = 0;
while(i < 50)
{
Cache_wbInvAll();
st_bef[i] = TSCL;
(*ptr);
st_aft[i] = TSCL;
i++;
}
i = 0;
while(i < 50)
{
printf("ch1 value is 0x%x 0x%x 0x%x\n",st_bef[i],st_aft[i],*ptr);
i++;
}
}
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Configured L1P and L1D as caches only(32KB each) and L2 as SRAM(512KB).
Configured stack, program and data regions in L2.
Observations:
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1. When I check the "Memory Browser" contents regarding the values in L1D cache for the st_bef[i] value, its not getting cleared even after cache invalidation. Can you please check why this happens?
2. As per the MSMC document(SPRUGW7A), I could see that each core has a port to access MSMCSRAM. So, when all the cores access MSMCSRAM, will
the read operation happen parallely?
