McASP polling works but Interrupt does not

Sherry Ismail

I am using LCDK C6748 to get stereo Audio In/out (a loop or echo routine). I initialise and start the McASP module according to the technical reference manual instructions. The AXR serialiser lines work fine in polling and without BIOS.... but if I use the exact same code in Interrupt service routine, AXR in TX/RX mode is dead. The ACLK, AFS, and AHCLK are fine in either case.

When I move from polling to Interrupt based program, these are the steps I take

1. I define the ISR routine, reference it in HWI in app.cfg (Associate McASP Event #61 to CPU interrupt #5)

2. The corresponding bit in IER register is enabled in main.c. ( to enabled GIE and IER)

3. I also enabled mcaspRegs->XINTCTL = 0x00000020; // RDATA ready
mcaspRegs->RINTCTL = 0;

The code for ISR is transmits 0x55555555 for slot 0 and 0x7FFFFFFF for Slot 1, since this is I2S serial line. (please ignore the RX buffer for now, i can't even get TX to transmit any value in interrupt mode)

void I2S_ISR(void) {
	Log_info0("Entered McASP isr");
	if (mcaspRegs->XSTAT & 0x00000020)		// If Tx data ready flag is up
			{
		if (mcaspRegs->XSTAT & 0x00000040)	// start of frame
				{
			mcaspRegs->XBUF7 = 0x55555555;
			mcaspRegs->XSTAT = 0x00000040;	// clear the start of frame flag
		} else if (mcaspRegs->XSTAT & 0x00000010)// if it is last slot of frame
				{
			mcaspRegs->XBUF7 = 0x7FFFFFFF;
			mcaspRegs->XSTAT = 0x00000010;	// clear last slot flag

		}
		mcaspRegs->XSTAT |= 0x00000020;	// clear XDATA flag
	}
}

Any help please?

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

I have suggestions for you are below and kindly valdate the same:

1. Start the Rx. & Tx. clocks after enabling error interrupts for McASP like

/* Enable error interrupts for McASP */

McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DATAREADY

| MCASP_TX_CLKFAIL

| MCASP_TX_SYNCERROR

| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DATAREADY

| MCASP_RX_CLKFAIL

| MCASP_RX_SYNCERROR

| MCASP_RX_OVERRUN);

/* Start the clocks */

McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);

McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);

2. Please ensure codec ISR mapping to CPU mask interrupt C674X_MASK_INT5 should be done before configuring the AIC31 codec for I2S mode:

IntRegister(C674X_MASK_INT5, Codec_ISR);

IntEventMap(C674X_MASK_INT5, SYS_INT_MCASP0_INT);

IntEnable(C674X_MASK_INT5);

3. In the McASPI2SConfigure(void) function code, activate the state machines after making sure that the XDATA bit is cleared to zero like below:

/* make sure that the XDATA bit is cleared to zero */

Kindly ensure to get INTx in the Interrupt vector table (i.e control is transferred to ISR - Codec_ISR() ).

while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */

McASPRxEnable(SOC_MCASP_0_CTRL_REGS);

McASPTxEnable(SOC_MCASP_0_CTRL_REGS);

4. I think, to enable Tx. and Rx. McASP interrupts, kindly ensure to configure McASP error interrupts through McASPTxIntEnable() & McASPRxIntEnable () which would trigger error interrupts if any.

mcasp->rintctl = 0x00000001; // overrun interrupt only

mcasp->xintctl = 0x00000020; // data interrupts

Kindly validate the above configuration and try it.

Thanks & regards,

Sivaraj K

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0 Sherry Ismail over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 885 points

I tried your recommended steps. Unfortunately, It still does not work. Using RTOS analyser, I can observe that the system goes into ISR of McASP because it displays Log_info() before and after the step of

mcaspRegs->XBUF7 = 0x55555555;

....when I pause it ( This indicates that it goes this line too.

It is AXR7 line on Pin 28 of J15 connector of LCDKC6748 kitC6748 DEV KIT schematics.pdf( just to remove the doubt that I am probing the incorrect pin on board).

The AFS and ACLK, AHCLK are working perfectly fine. But AXR7 ( serialiser 7) is dead.

Shall i zip my project and post it here? I have been trying for weeks trying to make McASP work on Interrupt.

0 Sherry Ismail over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 885 points

I could not do Step 3.. I do not have definitions .h files for Step (3) IntRegister(), IntEnable() etc. So I realised that my IER definition was not writing to CPU IER but a peripheral's IER... Can you please link the download page here?
interrupt.c is in ti/starterware_c6748 folder but somehow interrupt.h is not

0 Sherry Ismail over 9 years ago in reply to Sherry Ismail

Intellectual 885 points

Sivaraj , I get notification that you are replying. but your comments do not appear on the thread. Anyway, I realised that for TI RTOS, i do not need to set IER and CSR registers as this is taken care by app.cfg ( recalling a little from TI RTOS workshop).
I have added waiting while loops such as following

mcaspRegs->XSTAT = 0x00000040; // clear the start of frame flag
while (mcaspRegs->XSTAT & 0x00000040);    // wait till flag clear

Turns out, XSTAT does not allow to clear XDATA bit and it stays in Underrun condition as well . Any suggestions please?

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McASP polling works but Interrupt does not