Hi,
I am having trouble getting the EDMA controller to service McASP0 on an AM4379, running FreeRTOS with Startware/DAL drivers.
I have EDMA working for memory to memory DMA, including being triggered by the McASP0 Tx dma event (8)
The McASP0 is working fine in polling mode writing through the data port. I currently have 1 tx serialiser active, 2 slots, 32 bit per slot, 48Khz sample rate.
When the EDMA CC is setup to service the McASP0 tx dataport, I see that the first dma event is received by EDMA as the bCnt in the PaRAM is decremented by one. No further dma events are received however and the McASP triggers an UNDERRUN interrupt.
If I enable the McASP WRITE AFIFO (WNUMEVT = 1, WNUMDMA = 1) the result is exactly the same.
If I pre-load 64 words into the FIFO, I see 65 events being serviced by the EDMA (bCnt is decremented by 65), presumably one event each time a word written from the FIFO to the McASP, plus the original dma event from when the FIFO/McASP was enabled.
I have checked multiple times the PaRAM entry, which is:
OPT = 0x80108202 (PRIV | TCINTEN | TCC = 8 | FWID = 2 (32bit) | DAM (destination const addressing) )
SRC = local buffer in DDR3 or OCMC SRAM
ACNT = 4
BCNT = 512
DST = 0x46000000 (McASP0 dataport)
SRCBIDX = 4
DSTBIDX = 0
LINK = 0xFFFF
BCNTRLD = 0
SRCCIDX = 0
DSTCIDX = 0
CCNT = 1
I am using DMA channel 8, PaRAM index 8, event queue 0, shadow region 0. DMA is being triggered (I can see bCnt decrementing, and if I replace the PaRAM entry with a memory->memory dma I can verify that the McASP event is triggering it correctly.)
So my conclusion is that for some reason the EDMA cannot write to the McASP dataport. Things I have tried so far:
- disable MMU
- verify that the MMU has sensible permissions set for the McASP dataport address (MMU_MEM_ATTR_DEVICE_SHAREABLE, MMU_CACHE_POLICY_NON_CACHEABLE, MMU_ACCESS_CTRL_PRV_RW_USR_RW)
- triple check that the FIFO width bits in the OPT field of the PaRAM entry are set correctly to 32bit
Any suggestions would be greatly appreciated, thanks!
Kieran.
