Clipped audio out on beagleboard

Brian Watson49533

Other Parts Discussed in Thread: TPS65950, SYSCONFIG, SYSBIOS, OMAP3530, TPS65930

I've been working on an OS-less project (I couldn't stand the idea of using GDB - I have a much better debugger, and I needed very fast data abort and interrupt response) and been tackling the audio output side. I managed to get a waveform out at 44.1khz. It took me a while. However, the audio is clipped and I'm not sure why. It seems only the +ve side of the waveform gets clipped. The -ve side looks fine. I'm feeding in a sine wave (at 440hz) and the output looks totally consistent with the waveform except for the +ve side. It seems to be clipped at the 0v level.

I've tried fiddling with various level adjustments. I've changed fields such at ATX?1PGA, ARX?2PGA, ARX?2_APGA_GAIN, HSGAIN to no avail.

The audio is being DMAd to the TPS chip. When I dump the audio data out to a binary file it looks like a perfectly fine clean sinewave. It's 16 bit signed stereo PCM output.

Can anyone give a pointer to what may be going wrong? it's the last stage of the audio output I need to get working. I'm using the headset (AUDIO2) port.

Here's the TPS65950 configuration:

{0x49, REG_CODEC_MODE , 0x00}, // 0x01 - Disable for configuration

{0x49, REG_OPTION , OPTION_ARXL2_EN|OPTION_ARXR2_EN}, // 0x02 - Just audio out enabled

{0x49, REG_UNKNOWN , 0x00}, // 0x03

{0x49, REG_MICBIAS_CTL , 0x00}, // 0x04

{0x49, REG_ANAMICL , 0x00}, // 0x05

{0x49, REG_ANAMICR , 0x00}, // 0x06

{0x49, REG_AVADC_CTL , 0x00}, // 0x07

{0x49, REG_ADCMICSEL , 0x00}, // 0x08

{0x49, REG_DIGMIXING , 0x00}, // 0x09

{0x49, REG_ATXL1PGA , ATX_GAIN_0dB}, // 0x0a

{0x49, REG_ATXR1PGA , ATX_GAIN_0dB}, // 0x0b

{0x49, REG_AVTXL2PGA , 0x00}, // 0x0c

{0x49, REG_AVTXR2PGA , 0x00}, // 0x0d

{0x49, REG_AUDIO_IF , AUDIO_IF_AIF_EN|AUDIO_IF_DATA_WIDTH_16S16W}, // 0x0e

{0x49, REG_VOICE_IF , 0x00}, // 0x0f

{0x49, REG_ARXR1PGA , ARX_FGAIN_MUTE}, // 0x10

{0x49, REG_ARXL1PGA , ARX_FGAIN_MUTE}, // 0x11

{0x49, REG_ARXR2PGA , ARX_CGAIN_0dB|ARX_FGAIN_0dB}, // 0x12

{0x49, REG_ARXL2PGA , ARX_CGAIN_0dB|ARX_FGAIN_0dB}, // 0x13

{0x49, REG_VRXPGA , 0x00}, // 0x14

{0x49, REG_VSTPGA , 0x00}, // 0x15

{0x49, REG_VRX2ARXPGA , 0x00}, // 0x16

{0x49, REG_AVDAC_CTL , AVDAC_ADCR2_EN|AVDAC_ADCL2_EN}, // 0x17

{0x49, REG_ARX2VTXPGA , 0x00}, // 0x18

{0x49, REG_ARXL1_APGA_CTL , 0x00}, // 0x19

{0x49, REG_ARXR1_APGA_CTL , 0x00}, // 0x1a

{0x49, REG_ARXL2_APGA_CTL , ARX_APGA_GAIN_SET_NEG_6dB|ARX_APGA_DA_EN|ARX_APGA_PDZ}, // 0x1b

{0x49, REG_ARXR2_APGA_CTL , ARX_APGA_GAIN_SET_NEG_6dB|ARX_APGA_DA_EN|ARX_APGA_PDZ}, // 0x1c

{0x49, REG_ATX2ARXPGA , 0x00}, // 0x1d

{0x49, REG_BT_IF , 0x00}, // 0x1e

{0x49, REG_BTPGA , 0x00}, // 0x1f

{0x49, REG_BTSTPGA , 0x00}, // 0x20

{0x49, REG_EAR_CTL , 0x00}, // 0x21

{0x49, REG_HS_SEL , HS_SEL_HSOL_AL2_EN|HS_SEL_HSOR_AR2_EN}, // 0x22

{0x49, REG_HS_GAIN_SET , HS_GAIN_SET_HSL_GAIN_0dB|HS_GAIN_SET_HSR_GAIN_0dB}, // 0x23

{0x49, REG_HS_POPN_SET , 0x00}, // 0x24

{0x49, REG_PREDL_CTL , 0x00}, // 0x25

{0x49, REG_PREDR_CTL , 0x00}, // 0x26

{0x49, REG_PRECKL_CTL , 0x00}, // 0x27

{0x49, REG_PRECKR_CTL , 0x00}, // 0x28

{0x49, REG_HFL_CTL , 0x00}, // 0x29

{0x49, REG_HFR_CTL , 0x00}, // 0x2a

{0x49, REG_ALC_CTL , 0x00}, // 0x2b

{0x49, REG_ALC_SET1 , 0x00}, // 0x2c

{0x49, REG_ALC_SET2 , 0x00}, // 0x2d

{0x49, REG_BOOST_CTL , 0x00}, // 0x2e

{0x49, REG_SOFTVOL_CTL , 0x00}, // 0x2f

{0x49, REG_DTMF_FREQSEL , 0x00}, // 0x30

{0x49, REG_DTMF_TONEXT1H , 0x00}, // 0x31

{0x49, REG_DTMF_TONEXT1L , 0x00}, // 0x32

{0x49, REG_DTMF_TONEXT2H , 0x00}, // 0x33

{0x49, REG_DTMF_TONEXT2L , 0x00}, // 0x34

{0x49, REG_DTMF_TONOFF , 0x00}, // 0x35

{0x49, REG_DTMF_WANONOFF , 0x00}, // 0x36

{0x49, REG_I2S_RX_SCRAMBLE_H , 0x00}, // 0x37

{0x49, REG_I2S_RX_SCRAMBLE_M , 0x00}, // 0x38

{0x49, REG_I2S_RX_SCRAMBLE_L , 0x00}, // 0x39

{0x49, REG_APLL_CTL , APLL_CTL_APLL_EN|APLL_CTL_INFREQ_26Mhz}, // 0x3a

{0x49, REG_DTMF_CTL , 0x00}, // 0x3b

{0x49, REG_DTMF_PGA_CTL2 , 0x00}, // 0x3c

{0x49, REG_DTMF_PGA_CTL1 , 0x00}, // 0x3d

{0x49, REG_MISC_SET_1 , 0x00}, // 0x3e

{0x49, REG_PCMBTMUX , 0x00}, // 0x3f

{0x49, REG_UNUSED_0 , 0x00}, // 0x40

{0x49, REG_UNUSED_1 , 0x00}, // 0x41

{0x49, REG_UNUSED_2 , 0x00}, // 0x42

{0x49, REG_RX_PATH_SEL , 0x00}, // 0x43

{0x49, REG_VDL_APGA_CTL , 0x00}, // 0x44

{0x49, REG_VIBRA_CTL , 0x00}, // 0x45

{0x49, REG_VIBRA_SET , 0x00}, // 0x46

{0x49, REG_VIBRA_PWM_SET , 0x00}, // 0x47

{0x49, REG_ANAMIC_GAIN , 0x00}, // 0x48

{0x49, REG_MISC_SET_2 , 0x00}, // 0x49

{0x49, REG_CODEC_MODE , CODEC_MODE_APLL_RATE_44100|CODEC_MODE_CODECPDZ}, // 0x01 -- Must be done last when init complete

{0xff, 0xff, 0xff},

and the DMA configuration:

#define BITS_PER_SAMPLE 16

#define SAMPLES_PER_FRAME (128)

void audio_device::SetupDMA( void* pData, s32 Length )

{

g_pStereo = pData;

McBSP[2]->SPCR2 = BSP_SPCR2_FREE;

x_SleepThread( 100 );

McBSP[2]->SYSCONFIG = BSP_SYSCONFIG_ENAWAKEUP|BSP_SYSCONFIG_CLKACTIVITY_2|BSP_SYSCONFIG_SIDLEMODE_SMART;

McBSP[2]->THRSH2 = 1-1; // *((uint *) 0x49022090)

McBSP[2]->THRSH1 = 0x00000000; // *((uint *) 0x49022094)

McBSP[2]->XCCR = BSP_XCCR_XDMAEN;

McBSP[2]->RCCR = BSP_RCCR_RDISABLE;

McBSP[2]->RCR2 = 0;

McBSP[2]->RCR1 = 0;

McBSP[2]->XCR2 = BSP_XCR2_XPHASE|BSP_XCR2_XWDLEN_16|BSP_XCR2_XDATDLY1;

McBSP[2]->XCR1 = BSP_XCR1_XWDLEN_16; // 16 bit per word, should be the right audio channel?

McBSP[2]->SRGR2 = ((BITS_PER_SAMPLE*2-1)<<BSP_SRGR2_FPER_SHIFT)|BSP_SRGR2_CLKSM;

McBSP[2]->SRGR1 = (BITS_PER_SAMPLE-1)<<BSP_SRGR1_FWID_SHIFT;

McBSP[2]->PCR = BSP_PCR_CLKXP|BSP_PCR_FSXP;

McBSP[2]->SPCR2 = BSP_SPCR2_FREE;

McBSP[2]->SPCR1 = 0x00000000;

McBSP[2]->WAKEUPEN = BSP_WAKEUPEN_XRDYEN;

McBSP[2]->unused2 = 0x00000023; // ??? Unnamed*((uint *) 0x4902207c)

x_SleepThread( 100 );

McBSP[2]->SPCR2 = BSP_SPCR2_FREE|BSP_SPCR2_XRST;

#if defined(DMA_AUDIO)

g_pStereo = m_SampleBuffer;

// Set up all registers

DMA4->SDMA[DMA_CHANNEL].CCR = 0;

DMA4->SDMA[DMA_CHANNEL].CSR = 0x00001ffe; // Reset status register

DMA4->SDMA[DMA_CHANNEL].CEN = SAMPLES_PER_FRAME;

DMA4->SDMA[DMA_CHANNEL].CFN = sizeof(m_SampleBuffer)/sizeof(s16)/SAMPLES_PER_FRAME;

DMA4->SDMA[DMA_CHANNEL].CLNK_CTRL = DMA4_CLNK_CTRL_ENABLE_LINK|(DMA_CHANNEL);

DMA4->SDMA[DMA_CHANNEL].CICR = DMA4_CICR_LAST_IE; // End of frame interrupt

DMA4->SDMA[DMA_CHANNEL].CSSA = m_SampleBuffer; // Source data

DMA4->SDMA[DMA_CHANNEL].CDSA = &McBSP[2]->DXR; // Destination register

DMA4->SDMA[DMA_CHANNEL].CSDP = DMA4_CSDP_DATA_TYPE_16;

DMA4->SDMA[DMA_CHANNEL].CCR = (1<<DMA4_CCR_SYNC_CTRL_SHIFT)|

(1<<DMA4_CCR_SYNC_CTRL_UPPER_SHIFT)|

DMA4_CCR_SRC_AMODE_POST_INC|

DMA4_CCR_DST_AMODE_CONST|

DMA4_CCR_BUFFERING_DISABLE|

DMA4_CCR_WRITE_PRIORITY|

DMA4_CCR_ENABLE;

#endif

}

over 15 years ago

0 Brian Watson49533 over 15 years ago

Prodigy 20 points

struct

omap_dma4

{

volatile u32 IRQSTATUS[4];

// offset 0x0008

volatile u32 IRQENABLE[4];

// offset 0x0018

volatile u32 SYSSTATUS;

// offset 0x0028

volatile u32 OCP_SYSCONFIG;

// offset 0x002c

volatile u32 unused0[13];

// offset 0x0030 - 0x0063 unused

volatile u32 CAPS_0;

// offset 0x0064

volatile u32 unused1;

// offset 0x0068 unused

volatile u32 CAPS_2;

// offset 0x006c

volatile u32 CAPS_3;

// offset 0x0070

volatile u32 CAPS_4;

// offset 0x0074

volatile u32 GCR;

// offset 0x0078

volatile u32 unused2;

// offset 0x007c unused

// Should be 0x60 bytes

struct

{

volatile u32 CCR;

// offset 0x0080

volatile u32 CLNK_CTRL;

// offset 0x0084

volatile u32 CICR;

// offset 0x0088

volatile u32 CSR;

// offset 0x008c

volatile u32 CSDP;

// offset 0x0090

volatile u32 CEN;

// offset 0x0094

volatile u32 CFN;

// offset 0x0098

volatile void* CSSA;

// offset 0x009c

volatile void* CDSA;

// offset 0x00a0

volatile u32 CSE;

// offset 0x00a4

volatile u32 CSF;

// offset 0x00a8

volatile u32 CDE;

// offset 0x00ac

volatile u32 CDF;

// offset 0x00b0

volatile u32 CSAC;

// offset 0x00b4

volatile u32 CDAC;

// offset 0x00b8

volatile u32 CCEN;

// offset 0x00bc

volatile u32 CCFN;

// offset 0x00c0

volatile u32 COLOR;

// offset 0x00c4

volatile u32 unused0[6];

// offset 0x00c8 - 0xdf unused

}

SDMA

[32];

};

struct

omap_uart

{

volatile u32 RBR

;

volatile u32 IER

;

volatile u32 FCR

;

volatile u32 LCR

;

volatile u32 MCR

;

volatile u32 LSR

;

volatile u32 MSR

;

volatile u32 SCR

;

volatile u32 MDR1

;

volatile u32 MDR2

;

};

enum

uart_lsr

{

LSR_RX_FIFO_E

= (1<<0),

LSR_RX_OE

= (1<<1),

LSR_RX_PE

= (1<<2),

LSR_RX_FE

= (1<<3),

LSR_RX_BI

= (1<<4),

LSR_TX_FIFO_E

= (1<<5),

LSR_TX_SR_E

= (1<<6),

LSR_RX_FIFO_STS

= (1<<7),

};

enum

bsp_pcr_flags

{

BSP_PCR_CLKRP

= (1<<0),

BSP_PCR_CLKXP

= (1<<1),

BSP_PCR_FSRP

= (1<<2),

BSP_PCR_FSXP

= (1<<3),

BSP_PCR_DR_STAT

= (1<<4),

BSP_PCR_DX_STAT

= (1<<5),

BSP_PCR_CLKS_STAT

= (1<<6),

BSP_PCR_SCLKME

= (1<<7),

BSP_PCR_CLKRM

= (1<<8),

BSP_PCR_CLKXM

= (1<<9),

BSP_PCR_FSRM

= (1<<10),

BSP_PCR_FSXM

= (1<<11),

BSP_PCR_RIOEN

= (1<<12),

BSP_PCR_XIOEN

= (1<<13),

BSP_PCR_IDLE_EN

= (1<<14),

};

enum

bsp_spcr2_flags

{

BSP_SPCR2_XRST

= (1<<0),

BSP_SPCR2_XRDY

= (1<<1),

BSP_SPCR2_XEMPTY

= (1<<2),

BSP_SPCR2_XSYNCERR

= (1<<3),

BSP_SPCR2_XINTM = (1<<4),

// 2 bit field

BSP_SPCR2_GRST

= (1<<6),

BSP_SPCR2_FRST

= (1<<7),

BSP_SPCR2_SOFT

= (1<<8),

BSP_SPCR2_FREE

= (1<<9),

};

enum

bsp_xcr2_flags

{

BSP_XCR2_XDATDLY0 = (0<<0),

// 2 bit field

BSP_XCR2_XDATDLY1

= (1<<0),

BSP_XCR2_XDATDLY2

= (2<<0),

BSP_XCR2_XREVERSE = (1<<3),

// 2 bit field

BSP_XCR2_XWDLEN_8 = (0<<5),

// 3 bit field

BSP_XCR2_XWDLEN_12 = (1<<5),

// 3 bit field

BSP_XCR2_XWDLEN_16 = (2<<5),

// 3 bit field

BSP_XCR2_XWDLEN_20 = (3<<5),

// 3 bit field

BSP_XCR2_XWDLEN_24 = (4<<5),

// 3 bit field

BSP_XCR2_XWDLEN_32 = (5<<5),

// 3 bit field

BSP_XCR2_XFRLEN2_SHIFT = (8),

// 7 bit field

BSP_XCR2_XPHASE

= (1<<15),

};

enum

bsp_xcr1_flags

{

BSP_XCR1_XWDLEN_8 = (0<<5),

// 3 bit field

BSP_XCR1_XWDLEN_12 = (1<<5),

// 3 bit field

BSP_XCR1_XWDLEN_16 = (2<<5),

// 3 bit field

BSP_XCR1_XWDLEN_20 = (3<<5),

// 3 bit field

BSP_XCR1_XWDLEN_24 = (4<<5),

// 3 bit field

BSP_XCR1_XWDLEN_32 = (5<<5),

// 3 bit field

BSP_XCR1_XFRLEN1_SHIFT = (8),

// 7 bit field

};

enum

bsp_rccr_flags

{

BSP_RCCR_RDISABLE

= (1<<0),

BSP_RCCR_RDMAEN

= (1<<3),

BSP_RCCR_RFULL_CYCLE

= (1<<11),

};

enum

bsp_xccr_flags

{

BSP_XCCR_XDISABLE

= (1<<0),

BSP_XCCR_XDMAEN

= (1<<3),

BSP_XCCR_DLB

= (1<<5),

BSP_XCCR_XFULL_CYCLE

= (1<<11),

BSP_XCCR_DXENDLY_18NS = (0<<12),

// 2 bit field

BSP_XCCR_DXENDLY_26NS

= (1<<12),

BSP_XCCR_DXENDLY_35NS

= (2<<12),

BSP_XCCR_DXENDLY_42NS

= (3<<12),

BSP_XCCR_PPCONNECT

= (1<<14),

BSP_XCCR_EXTCLKGATE

= (1<<15),

};

enum

bsp_sysconfig_flags

{

BSP_SYSCONFIG_SOFTRESET

= (1<<1),

BSP_SYSCONFIG_ENAWAKEUP

= (1<<2),

BSP_SYSCONFIG_SIDLEMODE_FORCE = (0<<3),

// 2 bit field

BSP_SYSCONFIG_SIDLEMODE_NOIDLE

= (1<<3),

BSP_SYSCONFIG_SIDLEMODE_SMART

= (2<<3),

BSP_SYSCONFIG_CLKACTIVITY_0 = (0<<8),

// 2 bit field

BSP_SYSCONFIG_CLKACTIVITY_1

= (1<<8),

BSP_SYSCONFIG_CLKACTIVITY_2

= (2<<8),

BSP_SYSCONFIG_CLKACTIVITY_3

= (3<<8),

};

enum

bsp_irq_flags

{

BSP_IRQENABLE_RSYNCERREN

= (1<<0),

BSP_IRQENABLE_RFSREN

= (1<<1),

BSP_IRQENABLE_REOFEN

= (1<<2),

BSP_IRQENABLE_RRDYEN

= (1<<3),

BSP_IRQENABLE_RUNDFLEN

= (1<<4),

BSP_IRQENABLE_ROVFLEN

= (1<<5),

BSP_IRQENABLE_XSYNCERREN

= (1<<7),

BSP_IRQENABLE_XFSXEN

= (1<<8),

BSP_IRQENABLE_XEOFEN

= (1<<9),

BSP_IRQENABLE_XRDYEN

= (1<<10),

BSP_IRQENABLE_XUNDFLEN

= (1<<11),

BSP_IRQENABLE_XOVFLEN

= (1<<12),

BSP_IRQENABLE_XEMPTYEOFEN

= (1<<14),

};

enum

bsp_irqstatus_flags

{

BSP_IRQSTATUS_RSYNCERR

= (1<<0),

BSP_IRQSTATUS_RFSR

= (1<<1),

BSP_IRQSTATUS_REOF

= (1<<2),

BSP_IRQSTATUS_RRDY

= (1<<3),

BSP_IRQSTATUS_RUNDFLSTAT

= (1<<4),

BSP_IRQSTATUS_ROVFLSTAT

= (1<<5),

BSP_IRQSTATUS_XSYNCERR

= (1<<7),

BSP_IRQSTATUS_XFSX

= (1<<8),

BSP_IRQSTATUS_XEOF

= (1<<9),

BSP_IRQSTATUS_XRDY

= (1<<10),

BSP_IRQSTATUS_XUNDFLSTAT

= (1<<11),

BSP_IRQSTATUS_XOVFLSTAT

= (1<<12),

BSP_IRQSTATUS_XEMPTYEOF

= (1<<14),

};

enum

bsp_srgr2_flags

{

BSP_SRGR2_FPER_MASK

= 0x0fff,

BSP_SRGR2_FSGM

= (1<<12),

BSP_SRGR2_CLKSM

= (1<<13),

BSP_SRGR2_CLKSP

= (1<<14),

BSP_SRGR2_GSYNC

= (1<<15),

BSP_SRGR2_FPER_SHIFT

= 0,

};

enum

bsp_srgr1_flags

{

BSP_SRGR1_CLKGDV_SHIFT

= 0,

BSP_SRGR1_FWID_SHIFT

= 8,

};

enum

bsp_wakeupen_flags

{

BSP_WAKEUPEN_RSYNCERREN

= (1<<0),

BSP_WAKEUPEN_RFSREN

= (1<<1),

BSP_WAKEUPEN_REOFEN

= (1<<2),

BSP_WAKEUPEN_RRDYEN

= (1<<3),

BSP_WAKEUPEN_XSYNCERREN

= (1<<7),

BSP_WAKEUPEN_XFSXEN

= (1<<8),

BSP_WAKEUPEN_XEOFEN

= (1<<9),

BSP_WAKEUPEN_XRDYEN

= (1<<10),

BSP_WAKEUPEN_XEMPTYEOFEN

= (1<<14),

};

enum

dma4_csr_flags

{

DMA4_CSR_DROP = (1<<1),

// 0x0002

DMA4_CSR_HALF = (1<<2),

// 0x0004

DMA4_CSR_FRAME = (1<<3),

// 0x0008

DMA4_CSR_LAST = (1<<4),

// 0x0010

DMA4_CSR_BLOCK = (1<<5),

// 0x0020

DMA4_CSR_SYNC = (1<<6),

// 0x0040

DMA4_CSR_PKT = (1<<7),

// 0x0080

DMA4_CSR_TRANS_ERR = (1<<8),

// 0x0100

DMA4_CSR_SECURE_ERR = (1<<9),

// 0x0200

DMA4_CSR_SUPERVISOR_ERR = (1<<10),

// 0x0400

DMA4_CSR_MISALIGNED_ADRS_ERR = (1<<11),

// 0x0800

DMA4_CSR_DRAIN_END = (1<<12),

// 0x1000

};

enum

dma_ccr_flags

{

DMA4_CCR_SYNC_CTRL_SHIFT = 0,

// MASK 0x0000_001f

DMA4_CCR_FS = (1<<5),

// MASK 0x0000_0020

DMA4_CCR_READ_PRIORITY = (1<<6),

// MASK 0x0000_0040

DMA4_CCR_ENABLE = (1<<7),

// MASK 0x0000_0080

DMA4_CCR_SUSPEND_SENSITIVE = (1<<8),

// MASK 0x0000_0100

DMA4_CCR_RD_ACTIVE = (1<<9),

// MASK 0x0000_0200

DMA4_CCR_WR_ACTIVE = (1<<10),

// MASK 0x0000_0400

DMA4_CCR_SRC_AMODE_CONST = (0<<12),

// MASK 0x0000_3000

DMA4_CCR_SRC_AMODE_POST_INC

= (1<<12),

DMA4_CCR_SRC_AMODE_SINGLE_INDEX

= (2<<12),

DMA4_CCR_SRC_AMODE_DOUBLE_INDEX

= (3<<12),

DMA4_CCR_DST_AMODE_CONST = (0<<14),

// MASK 0x0000_C000

DMA4_CCR_DST_AMODE_POST_INC

= (1<<14),

DMA4_CCR_DST_AMODE_SINGLE_INDEX

= (2<<14),

DMA4_CCR_DST_AMODE_DOUBLE_INDEX

= (3<<14),

DMA4_CCR_CONST_FILL_ENABLE = (1<<16),

// MASK 0x0001_0000

DMA4_CCR_TRANSPARENT_COPY_ENABLE= (1<<17),

// MASK 0x0002_0000

DMA4_CCR_BS = (1<<18),

// MASK 0x0004_0000

DMA4_CCR_SYNC_CTRL_UPPER_SHIFT = (19),

// MASK 0x0018_0000

DMA4_CCR_SECURE = (1<<21),

// MASK 0x0020_0000

DMA4_CCR_SUPERVISOR = (1<<22),

// MASK 0x0040_0000

DMA4_CCR_PREFETCH = (1<<23),

// MASK 0x0080_0000

DMA4_CCR_SEL_SRC_DST_SYNC = (1<<24),

// MASK 0x0100_0000

DMA4_CCR_BUFFERING_DISABLE = (1<<25),

// MASK 0x0200_0000

DMA4_CCR_WRITE_PRIORITY = (1<<26),

// MASK 0x0400_0000

};

enum

dma_cicr_flags

{

DMA4_CICR_DROP_IE = (1<<1),

// 0x0002

DMA4_CICR_HALF_IE = (1<<2),

// 0x0004

DMA4_CICR_FRAME_IE = (1<<3),

// 0x0008

DMA4_CICR_LAST_IE = (1<<4),

// 0x0010

DMA4_CICR_BLOCK_IE = (1<<5),

// 0x0020

DMA4_CICR_PKT_IE = (1<<7),

// 0x0080

DMA4_CICR_TRANS_ERR_IE = (1<<8),

// 0x0100

DMA4_CICR_SECURE_ERR_IE = (1<<9),

// 0x0200

DMA4_CICR_SUPERVISOR_ERR_IE = (1<<10),

// 0x0400

DMA4_CICR_MISALIGNED_ERR_IE = (1<<11),

// 0x0800

DMA4_CICR_DRAIN_IE = (1<<12),

// 0x1000

};

enum

dma_csdp_flags

{

DMA4_CSDP_DATA_TYPE_8

= (0<<0),

DMA4_CSDP_DATA_TYPE_16

= (1<<0),

DMA4_CSDP_DATA_TYPE_32

= (2<<0),

DMA4_CSDP_SRC_PACKED

= (1<<6),

DMA4_CSDP_SRC_BURST_EN_SINGLE

= (0<<7),

DMA4_CSDP_SRC_BURST_EN_16

= (1<<7),

DMA4_CSDP_SRC_BURST_EN_32

= (2<<7),

DMA4_CSDP_SRC_BURST_EN_64

= (3<<7),

DMA4_CSDP_DST_PACKED

= (1<<13),

DMA4_CSDP_DST_BURST_EN_SINGLE

= (0<<14),

DMA4_CSDP_DST_BURST_EN_16

= (1<<14),

DMA4_CSDP_DST_BURST_EN_32

= (2<<14),

DMA4_CSDP_DST_BURST_EN_64

= (3<<14),

DMA4_CSDP_DST_ENDIAN_LOCK

= (1<<18),

DMA4_CSDP_DST_LITTLE_ENDIAN

= (0<<19),

DMA4_CSDP_DST_BIG_ENDIAN

= (1<<19),

DMA4_CSDP_SRC_ENDIAN_LOCK

= (1<<20),

DMA4_CSDP_SRC_LITTLE_ENDIAN

= (0<<21),

DMA4_CSDP_SRC_BIG_ENDIAN

= (1<<21),

};

enum

dma_clnk_ctrl_flags

{

DMA4_CLNK_CTRL_ENABLE_LINK

= (1<<15),

DMA4_CLNK_CTRL_NEXTLCH_ID

= 0,

};

enum

audio_i2s_registers

{

REG_CODEC_MODE

= 0x1,

REG_OPTION

= 0x2,

REG_UNKNOWN

= 0x3,

REG_MICBIAS_CTL

= 0x4,

REG_ANAMICL

= 0x5,

REG_ANAMICR

= 0x6,

REG_AVADC_CTL

= 0x7,

REG_ADCMICSEL

= 0x8,

REG_DIGMIXING

= 0x9,

REG_ATXL1PGA

= 0xA,

REG_ATXR1PGA

= 0xB,

REG_AVTXL2PGA

= 0xC,

REG_AVTXR2PGA

= 0xD,

REG_AUDIO_IF

= 0xE,

REG_VOICE_IF

= 0xF,

REG_ARXR1PGA

= 0x10,

REG_ARXL1PGA

= 0x11,

REG_ARXR2PGA

= 0x12,

REG_ARXL2PGA

= 0x13,

REG_VRXPGA

= 0x14,

REG_VSTPGA

= 0x15,

REG_VRX2ARXPGA

= 0x16,

REG_AVDAC_CTL

= 0x17,

REG_ARX2VTXPGA

= 0x18,

REG_ARXL1_APGA_CTL

= 0x19,

REG_ARXR1_APGA_CTL

= 0x1A,

REG_ARXL2_APGA_CTL

= 0x1B,

REG_ARXR2_APGA_CTL

= 0x1C,

REG_ATX2ARXPGA

= 0x1D,

REG_BT_IF

= 0x1E,

REG_BTPGA

= 0x1F,

REG_BTSTPGA

= 0x20,

REG_EAR_CTL

= 0x21,

REG_HS_SEL

= 0x22,

REG_HS_GAIN_SET

= 0x23,

REG_HS_POPN_SET

= 0x24,

REG_PREDL_CTL

= 0x25,

REG_PREDR_CTL

= 0x26,

REG_PRECKL_CTL

= 0x27,

REG_PRECKR_CTL

= 0x28,

REG_HFL_CTL

= 0x29,

REG_HFR_CTL

= 0x2A,

REG_ALC_CTL

= 0x2B,

REG_ALC_SET1

= 0x2C,

REG_ALC_SET2

= 0x2D,

REG_BOOST_CTL

= 0x2E,

REG_SOFTVOL_CTL

= 0x2F,

REG_DTMF_FREQSEL

= 0x30,

REG_DTMF_TONEXT1H

= 0x31,

REG_DTMF_TONEXT1L

= 0x32,

REG_DTMF_TONEXT2H

= 0x33,

REG_DTMF_TONEXT2L

= 0x34,

REG_DTMF_TONOFF

= 0x35,

REG_DTMF_WANONOFF

= 0x36,

REG_I2S_RX_SCRAMBLE_H

= 0x37,

REG_I2S_RX_SCRAMBLE_M

= 0x38,

REG_I2S_RX_SCRAMBLE_L

= 0x39,

REG_APLL_CTL

= 0x3A,

REG_DTMF_CTL

= 0x3B,

REG_DTMF_PGA_CTL2

= 0x3C,

REG_DTMF_PGA_CTL1

= 0x3D,

REG_MISC_SET_1

= 0x3E,

REG_PCMBTMUX

= 0x3F,

REG_UNUSED_0

= 0x40,

REG_UNUSED_1

= 0x41,

REG_UNUSED_2

= 0x42,

REG_RX_PATH_SEL

= 0x43,

REG_VDL_APGA_CTL

= 0x44,

REG_VIBRA_CTL

= 0x45,

REG_VIBRA_SET

= 0x46,

REG_VIBRA_PWM_SET

= 0x47,

REG_ANAMIC_GAIN

= 0x48,

REG_MISC_SET_2

= 0x49,

REG_SW_SHADOW

= 0x4A,

};

enum

i2s_audio_codec_mode

{

CODEC_MODE_APLL_RATE

= 0xF0,

CODEC_MODE_APLL_RATE_8000

= 0x00,

CODEC_MODE_APLL_RATE_11025

= 0x10,

CODEC_MODE_APLL_RATE_12000

= 0x20,

CODEC_MODE_APLL_RATE_16000

= 0x40,

CODEC_MODE_APLL_RATE_22050

= 0x50,

CODEC_MODE_APLL_RATE_24000

= 0x60,

CODEC_MODE_APLL_RATE_32000

= 0x80,

CODEC_MODE_APLL_RATE_44100

= 0x90,

CODEC_MODE_APLL_RATE_48000

= 0xA0,

CODEC_MODE_APLL_RATE_96000

= 0xE0,

CODEC_MODE_SEL_16K

= 0x08,

CODEC_MODE_CODECPDZ

= 0x02,

CODEC_MODE_OPT_MODE

= 0x01,

CODEC_MODE_OPTION_1

= (1 << 0),

CODEC_MODE_OPTION_2

= (0 << 0),

};

enum

i2s_audio_option

{

OPTION_ATXL1_EN

= (1<<0),

OPTION_ATXR1_EN

= (1<<1),

OPTION_ATXI2_VTXL_EN

= (1<<2),

OPTION_ATXI2_VTXR_EN

= (1<<3),

OPTION_ARXL1_VRX_EN

= (1<<4),

OPTION_ARXR1_EN

= (1<<5),

OPTION_ARXL2_EN

= (1<<6),

OPTION_ARXR2_EN

= (1<<7),

};

enum

i2s_audio_avadc_ctl

{

AVADC_CTL_ADCR_EN

= (1<<1),

AVADC_CTL_CLK_PRIORITY

= (1<<2),

AVADC_CTL_ADCL_EN

= (1<<3),

};

enum

i2s_audio_avdac_ctl

{

AVDAC_ADACR1_EN

= (1<<0),

AVDAC_ADACL1_EN

= (1<<1),

AVDAC_ADACR2_EN

= (1<<2),

AVDAC_ADACL2_EN

= (1<<3),

AVDAC_VDAC_EN

= (1<<4),

};

enum

i2s_audio_voice_if

{

AUDIO_IF_AIF_EN

= (1<<0),

AUDIO_IF_CLK256FS_EN

= (1<<1),

AUDIO_IF_TRI_EN

= (1<<2),

AUDIO_IF_FORMAT_CODEC_MODE

= (0<<3),

AUDIO_IF_FORMAT_LEFT_JUSTIFIED

= (1<<3),

AUDIO_IF_FORMAT_RIGHT_JUSTIFIED

= (2<<3),

AUDIO_IF_FORMAT_TDM

= (3<<3),

AUDIO_IF_DATA_WIDTH_16S16W

= (0<<5),

AUDIO_IF_DATA_WIDTH_32S16W

= (2<<5),

AUDIO_IF_DATA_WIDTH_32S32W

= (3<<5),

AUDIO_IF_AIF_SLAVE_EN

= (1<<7),

};

enum

i2s_audio_arx

{

ARX_CGAIN_0dB

= (0<<6),

ARX_CGAIN_6dB

= (1<<6),

ARX_CGAIN_12dB

= (2<<6),

ARX_FGAIN_MUTE

= (0<<0),

ARX_FGAIN_NEG_62dB

= (1<<0),

ARX_FGAIN_NEG_61dB

= (2<<0),

ARX_FGAIN_NEG_60dB

= (3<<0),

ARX_FGAIN_NEG_59dB

= (4<<0),

ARX_FGAIN_NEG_58dB

= (5<<0),

ARX_FGAIN_NEG_57dB

= (6<<0),

ARX_FGAIN_NEG_56dB

= (7<<0),

ARX_FGAIN_NEG_55dB

= (8<<0),

ARX_FGAIN_NEG_54dB

= (9<<0),

ARX_FGAIN_NEG_53dB

= (10<<0),

ARX_FGAIN_NEG_52dB

= (11<<0),

ARX_FGAIN_NEG_51dB

= (12<<0),

ARX_FGAIN_NEG_50dB

= (13<<0),

ARX_FGAIN_NEG_49dB

= (14<<0),

ARX_FGAIN_NEG_48dB

= (15<<0),

ARX_FGAIN_NEG_47dB

= (16<<0),

ARX_FGAIN_NEG_46dB

= (17<<0),

ARX_FGAIN_NEG_45dB

= (18<<0),

ARX_FGAIN_NEG_44dB

= (19<<0),

ARX_FGAIN_NEG_43dB

= (20<<0),

ARX_FGAIN_NEG_42dB

= (21<<0),

ARX_FGAIN_NEG_41dB

= (22<<0),

ARX_FGAIN_NEG_40dB

= (23<<0),

ARX_FGAIN_NEG_39dB

= (24<<0),

ARX_FGAIN_NEG_38dB

= (25<<0),

ARX_FGAIN_NEG_37dB

= (26<<0),

ARX_FGAIN_NEG_36dB

= (27<<0),

ARX_FGAIN_NEG_35dB

= (28<<0),

ARX_FGAIN_NEG_34dB

= (29<<0),

ARX_FGAIN_NEG_33dB

= (30<<0),

ARX_FGAIN_NEG_32dB

= (31<<0),

ARX_FGAIN_NEG_31dB

= (32<<0),

ARX_FGAIN_NEG_30dB

= (33<<0),

ARX_FGAIN_NEG_29dB

= (34<<0),

ARX_FGAIN_NEG_28dB

= (35<<0),

ARX_FGAIN_NEG_27dB

= (36<<0),

ARX_FGAIN_NEG_26dB

= (37<<0),

ARX_FGAIN_NEG_25dB

= (38<<0),

ARX_FGAIN_NEG_24dB

= (39<<0),

ARX_FGAIN_NEG_23dB

= (40<<0),

ARX_FGAIN_NEG_22dB

= (41<<0),

ARX_FGAIN_NEG_21dB

= (42<<0),

ARX_FGAIN_NEG_20dB

= (43<<0),

ARX_FGAIN_NEG_19dB

= (44<<0),

ARX_FGAIN_NEG_18dB

= (45<<0),

ARX_FGAIN_NEG_17dB

= (46<<0),

ARX_FGAIN_NEG_16dB

= (47<<0),

ARX_FGAIN_NEG_15dB

= (48<<0),

ARX_FGAIN_NEG_14dB

= (49<<0),

ARX_FGAIN_NEG_13dB

= (50<<0),

ARX_FGAIN_NEG_12dB

= (51<<0),

ARX_FGAIN_NEG_11dB

= (52<<0),

ARX_FGAIN_NEG_10dB

= (53<<0),

ARX_FGAIN_NEG_9dB

= (54<<0),

ARX_FGAIN_NEG_8dB

= (55<<0),

ARX_FGAIN_NEG_7dB

= (56<<0),

ARX_FGAIN_NEG_6dB

= (57<<0),

ARX_FGAIN_NEG_5dB

= (58<<0),

ARX_FGAIN_NEG_4dB

= (59<<0),

ARX_FGAIN_NEG_3dB

= (60<<0),

ARX_FGAIN_NEG_2dB

= (61<<0),

ARX_FGAIN_NEG_1dB

= (62<<0),

ARX_FGAIN_0dB

= (63<<0),

};

enum

i2s_audio_atx

{

ATX_GAIN_0dB

= (0<<0),

ATX_GAIN_1dB

= (1<<0),

ATX_GAIN_2dB

= (2<<0),

ATX_GAIN_3dB

= (3<<0),

ATX_GAIN_4dB

= (4<<0),

ATX_GAIN_5dB

= (5<<0),

ATX_GAIN_6dB

= (6<<0),

ATX_GAIN_7dB

= (7<<0),

ATX_GAIN_8dB

= (8<<0),

ATX_GAIN_9dB

= (9<<0),

ATX_GAIN_10dB

= (10<<0),

ATX_GAIN_11dB

= (11<<0),

ATX_GAIN_12dB

= (12<<0),

ATX_GAIN_13dB

= (13<<0),

ATX_GAIN_14dB

= (14<<0),

ATX_GAIN_15dB

= (15<<0),

ATX_GAIN_16dB

= (16<<0),

ATX_GAIN_17dB

= (17<<0),

ATX_GAIN_18dB

= (18<<0),

ATX_GAIN_19dB

= (19<<0),

ATX_GAIN_20dB

= (20<<0),

ATX_GAIN_21dB

= (21<<0),

ATX_GAIN_22dB

= (22<<0),

ATX_GAIN_23dB

= (23<<0),

ATX_GAIN_24dB

= (24<<0),

ATX_GAIN_25dB

= (25<<0),

ATX_GAIN_26dB

= (26<<0),

ATX_GAIN_27dB

= (27<<0),

ATX_GAIN_28dB

= (28<<0),

ATX_GAIN_29dB

= (29<<0),

ATX_GAIN_30dB

= (30<<0),

ATX_GAIN_31dB

= (31<<0),

};

enum

i2s_apll_ctl

{

APLL_CTL_APLL_EN

= (1<<4),

APLL_CTL_INFREQ_19_2Mhz

= (5<<0),

APLL_CTL_INFREQ_26Mhz

= (6<<0),

APLL_CTL_INFREQ_38_4Mhz

= (15<<0),

};

enum

i2s_hs_sel

{

HS_SEL_HSOL_VOICE_EN

= (1<<0),

HS_SEL_HSOL_AL1_EN

= (1<<1),

HS_SEL_HSOL_AL2_EN

= (1<<2),

HS_SEL_HSOR_VOICE_EN

= (1<<3),

HS_SEL_HSOR_AR1_EN

= (1<<4),

HS_SEL_HSOR_AR2_EN

= (1<<5),

HS_SEL_HS_OUTLOW_EN

= (1<<6),

HS_SEL_HSR_INV_EN

= (1<<7),

};

enum

i2s_hs_gain_set

{

HS_GAIN_SET_HSL_GAIN_POWERDOWN

= (0<<0),

HS_GAIN_SET_HSL_GAIN_6dB

= (1<<0),

HS_GAIN_SET_HSL_GAIN_0dB

= (2<<0),

HS_GAIN_SET_HSL_GAIN_NEG_6dB

= (3<<0),

HS_GAIN_SET_HSR_GAIN_POWERDOWN

= (0<<2),

HS_GAIN_SET_HSR_GAIN_6dB

= (1<<2),

HS_GAIN_SET_HSR_GAIN_0dB

= (2<<2),

HS_GAIN_SET_HSR_GAIN_NEG_6dB

= (3<<2),

};

enum

i2s_arx_apga_ctl

{

ARX_APGA_PDZ

= (1<<0),

ARX_APGA_DA_EN

= (1<<1),

ARX_APGA_FM_EN

= (1<<2),

ARX_APGA_GAIN_SET_12dB

= (0<<3),

ARX_APGA_GAIN_SET_10dB

= (1<<3),

ARX_APGA_GAIN_SET_8dB

= (2<<3),

ARX_APGA_GAIN_SET_6dB

= (3<<3),

ARX_APGA_GAIN_SET_4dB

= (4<<3),

ARX_APGA_GAIN_SET_2dB

= (5<<3),

ARX_APGA_GAIN_SET_0dB

= (6<<3),

ARX_APGA_GAIN_SET_NEG_2dB

= (7<<3),

ARX_APGA_GAIN_SET_NEG_4dB

= (8<<3),

ARX_APGA_GAIN_SET_NEG_6dB

= (9<<3),

ARX_APGA_GAIN_SET_NEG_8dB

= (10<<3),

ARX_APGA_GAIN_SET_NEG_10dB

= (11<<3),

ARX_APGA_GAIN_SET_NEG_12dB

= (12<<3),

ARX_APGA_GAIN_SET_NEG_14dB

= (13<<3),

ARX_APGA_GAIN_SET_NEG_16dB

= (14<<3),

ARX_APGA_GAIN_SET_NEG_18dB

= (15<<3),

ARX_APGA_GAIN_SET_NEG_20dB

= (16<<3),

ARX_APGA_GAIN_SET_NEG_22dB

= (17<<3),

ARX_APGA_GAIN_SET_NEG_24dB

= (18<<3),

0 Mewada Nitin over 14 years ago in reply to Brian Watson49533

Intellectual 340 points

HI Brian,

Let me tell you what i am using for m work.

1.Beagleboard omap 3530 Rev B

2.CCSv5.0.2.00006 version

3.XDS100v2 Emulator

4.WIndow Xp or window 7.

Now what i want is that i want to read the audio file file from MMC card/USB Host ..kind of thing. Let's say some kind of external memory right. Then i want to decode that file and play through the a output port given in the board.

Basically my intention was to use SYSBIOS(BIOS 6) and to get the environment of it, but i think it will not work. So i am thinking to use DSP/BIOS 5 in CCS.

So, what i was thinking that i need to learn how to read from external memory then i need mp3 codec, finally MCBSP driver to drive to output port. This dual core is something new to me and only i had experience in single core DSP side.

Recently i had worked with basic programs using SYSBIOS in CCS5 using OMAP3530 and i am getting good results too. Here problem is the same as yours, there is no driver available for DMA,MCBSP and for other peripheral for the SYSBIOS plateform without using linux ,codec engine, and PSP packages.

Is there any way that you can simply guide me. If you are not aware of Texas Instruments software , then let me know

With Regards

Nitin Mewada

0 santosh vastrad over 13 years ago

Expert 2060 points

HI Brain,

Have got solved you issue?

same thing i'm doing in uboot source code,

i2c1 configuration for tps65930 audio codec,

and mcbsp2 registers for audio file raw data sending,

so please suggest me, why i'm not able to listen any music, only tuck sound hearing?

regards,

santosh vastrad

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Clipped audio out on beagleboard