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EMIF16/UPP bus

pascal wilner
Prodigy 215 points
Other Parts Discussed in Thread: TMS320C6655

Hi For new design I use TMS320C6655. To interface my FPGA I need EMIF16 16 bit asynchronous bus for access internal registers inside FPGA and also I need UPP 16 bit synchronous bus to transfer data from internal FIFO inside FPGA directly to DDR3 of the DSP using DMA . QUESTION : I see that pins of DSP are dual fonction : EMIF16/UPP so is it possible for both transfer I defined bellow and how I control the definition of dual pin ? ]

  • 0
    TI__Mastermind 43660 points
    Pascal,

    The C6655 device wasn't really designed to be dynamically switched back and forth between EMIF and uPP. I'm guessing you'll have to do some additional configuration each time you switch between the two. There are a number of interfaces available that would allow communications with the FPGA. Would you consider using SPI for their IO register interface? That wouldn't add many pins and would simplify your logic design.

    Please note we have not yet explored a way to use both the interfaces in a design. If you still want to do that, you may have to come up with your own configurations.

    Hope it clarifies.

    Regards,
    Senthil
  • 0
    TI__Guru* 81335 points

    Hi Pascal Wilner,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    Thank you.

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 215 points

    Mr Senthil

    Thanks a lot for professional answer.

    I will follow your recommendations.

    pascal