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DSP C66 how to access timer on AM57X

Other Parts Discussed in Thread: OMAPL138, AM5728

Dear all,

My platform is AM57x.

I want to write a code to access timer2 by dsp (c66).

Is any document or sample code for reference?

  • Hi Descent Sung,

    You need download the Processor SDK released for AM57x software development. The PDK of PSDK should have code you are looking for.

    www.ti.com/.../PROCESSOR-SDK-AM57X

    The AM57x devices are supported in Sitara forum so moving this thread over there.

    Thank you.
  • Dear all,

    I reference omapl138 timer, it can be set to chained mode, so I can let the counter to add 1 every 1us.
    Can I do the this on AM57x platform, If I want to set the timer counter to add 1 every 1us?

    Thank you.
  • Hi,

    What SDK are you using?
  • Hi,

    I download ti-processor-sdk-rtos-am57xx-evm-02.00.00.00-Linux-x86-Install.bin .

    Any sample can be reference?

  • Hi,

    AM572x timer can work in Timer, Capture & Compare mode (see Sections 22.2.4.6 Timer Mode Functionality through 22.2.4.11 Timer Counting Rate from device TRM).
    For your question in particular:
    Yes, you can use the timer to increment (with 1) every 1 second, timer mode functionality can be utilized for this. There is no linux example for this. You can refer to RTOS sources & modify the timer examples accordingly (even port them on your linux setup).

    Best Regards,
    Yordan
  • Hi Yordan,

    22.2.4.6 part I already read, I will read again to find more information.

    I just find the table 22-10 in am572x datasheet, it can "interrupt" by 37h, 2s, 500us, 62.5 us, but I want to increment (with 1) every 1us, not 1 second.

    Because omapl138 have chained mode to set it, but I don't find the chained mode for my purpose in am572x datasheet.

    I want to find the overall clocking diagram like omapl138 in am572x datasheet, but I don't find.

    Do something I miss?

  • Hi, 

    descent sung said:

    I want to find the overall clocking diagram like omapl138 in am572x datasheet, but I don't find.

    Do something I miss?

     

    Please use AM57xx Clock Tree Tool & PRCM chapter in TRM: 
      

    Best Regards, 
    Yordan

  • Hi Yordan,

    I have installed the ctt, but it is difficulty to use, the am572x diagram is vary large.
    It is not convenience to scroll the diagram.
    If a diagram that is like omapl138 is convenience.

    Thank you.
  • Hi,

    The clock tree structure of AM57xx devices is more complex than the device you reference (omapl138).
    You can find timer 2 clock sources in Figure 3-48. CM_CORE_AON_TIMER2 Clock Manager Overview in AM57xx TRM, and if you wish to go further into the clock tree, you need to search where each time2 source comes from and so on.
    This is why CTT was created for these devices. You can select the desired module, in your case Timer2, and from the drop-down menus of the tool you can make it show only the clock structure of that module.

    Best Regards,
    Yordan
  • Hi Yordan,

    Regarding this 1us increment in counter issue, OMAPL138 uses chained mode to let the timer counters.

    I cannot find this kind of feature in AM5728 GPTimer.

    I checked the AM57GPEVM clocksource is default as below:

    So I can only get a 50ns time period, and it will not get a 1us = 1000ns increment in TCRR even with the prescalers from 2 to 256.

    50ns * 16 = 800ns

    50ns * 32 = 1600ns

    Am I right??

    other clock sources is 22.5Mhz and 32.768Khz. All cannot match the 1Mhz clock with the divisor 2-256.

    In conclusion,

    Is this mean I have to use a external reference clock 0~3 for this application on AM5728 GPEVM? (1us incrementation of TCRR)

    Please advise.

    Thank you.

  • Hi,

    Which timer do you use, and what clock frequency do you want to achieve?
    It is true that you can use 20MHz, 22,5MHz or 32,768KHz clock sources, but you can use different path (one that has dividers) to supply the Timer FCLK.

    I.e. I used CTT to configure TIMER4_FCLK to be 2.5 MHz clock. For the purpose I used the ABE_GICLK (supplied by DPLL_ABE) and a 20MHz source on SYS_CLK1. On the path I have 3 clock dividers (Divider_ABE_CLK, Divider_AESS_FCLK & Divider_ABE_GICLK), which I set to 2. So maybe you can choose a different (more appropriate) path to feed your timer fclk.

    Best Regards,
    Yordan
  • Hi Yordan,

    Thanks for your quickly reply.
    I checked what you mentioned, but these divisor are all the power of 2s.
    Which means I still get 20Mhz, 10Mhz, 5Mhz, 2.5Mhz, 1.25Mhz ..... same as period I mentiond : 50ns x prescaler(power of 2).
    Is there some other divisors I missed for more flexible adjusting the period?

    Thank you for kindly help.